A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder

Kutaragi, K.; Suzuoki, M.; Hiroi, T.; Magoshi, Hidetaka; Okamoto, Satoru; Oka, Masaaki; Ohba, A.; Yamamoto, Yasuyuki; Furuhashi, Makoto; Tanaka, Masamitsu; Tanaka, Yutaka; Okada, Tomoyuki; Nagamatsu, M.; Urakawa, Y.; Funyu, M.; Kunimatsu, Atsushi; Goto, Hiroaki; Hashimoto, Koki; Ide, N.; Murakami, Hiroaki; Ohtaguro, Y.; Aono, A.

doi:10.1109/4.799870

Cited by 30 publications

(11 citation statements)

References 1 publication

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“…Until recently, few of these architectural concepts made it into mainstream processor designs, but the increasingly stringent power/performance requirements for embedded systems have resulted in a number of recent implementations that have adopted these concepts. Chips like the Sony Emotion Engine [20,23,29] and Intel's MXP5800 both achieved high performance at low power by adopting three levels (registers, local memory, external DRAM) of softwaremanaged memory. More recently, the STI Cell processor has adopted a similar approach where data movement between Figure 1: Overview of the Cell processor these three address spaces is explicitly controlled by the application.…”

Section: Related Workmentioning

confidence: 99%

The potential of the cell processor for scientific computing

Williams

Shalf

Oliker

et al. 2006

Proceedings of the 3rd Conference on Computing Frontiers

241

147

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The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the forthcoming STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on the Cell full system simulator. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

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Section: Related Workmentioning

confidence: 99%

The potential of the cell processor for scientific computing

Williams

Shalf

Oliker

et al. 2006

Proceedings of the 3rd Conference on Computing Frontiers

241

147

View full text Add to dashboard Cite

show abstract

“…Thus, not only contention and access latency are reduced but also the data transfer time can be hidden. A clear example is the processor of the PlayStation 2 videogaming system [9], composed by a main general purpose core, two vector units and a scratch-pad memory in which data are moved through a programmable DMA controller. The Cell processor [7] from Sony, IBM and Toshiba is the ideal successor of that design.…”

Section: Related Workmentioning

confidence: 99%

Lightweight DMA management mechanisms for multiprocessors on FPGA

Tumeo

Monchiero

Palermo

et al. 2008

2008 International Conference on Application-Specific Systems, Architectures and Processors

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This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each processor. The system integrates all standard DMA primitives via a fast Application Programming Interface (API) and relies on interrupts having also the possibility to manage a command list. This interface allows to program the embedded multiprocessor architecture on FPGA with simple DMAs using the same DMA techniques adopted on high performance multiprocessors with complex DMA controllers. Several experiments demonstrate the performance of our solution, allowing 57% improvement on the execution time of a selected set of benchmarks. We furthermore show how some DMA programming techniques (double and multi-buffering) can be effectively used within our platform, thus easing the design and development of the hardware and the software in a reconfigurable DMA-based environment. 1

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“…The architecture space of such systems varies greatly and typically includes a mid/high-performance scalar processor executing the OS, I/O and high-level data flow scheduling, complemented by a number of programmable or hardwired custom accelerators tuned to accelerate certain core functions of the target application [2]. These accelerators occasionally are custom VLIW engines as the VLIW architectural paradigm [3] seems to be the most promising in delivering very high single-processor performance, particularly on data-parallel inner loops; interestingly enough, such processors seem to be finding niche markets in behavioral (ESL) synthesis as a core component of the underlying VLSI platform [4].…”

Section: Introductionmentioning

confidence: 99%

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

Stevens

Chouliaras

2010

2010 IEEE Computer Society Annual Symposium on VLSI

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We discuss LE1, a parameterized VLIW Chip Multiprocessor (CMP) adhering to the shared memory programmers model. LE1's novelty lies in its ability to perform dynamic thread-spawning through hardware support for PThread-like primitives in addition to its substantial architectural and microarchitectural parameterization. Dynamic (hardware) thread creation is very fast and removes the need for an executive/OS, presenting to the application programmer a 'bare-metal' multiprocessor, capable of exploiting all forms of parallelism. The core LE1 CPU is a configurable, 8-stage pipeline VLIW engine with a proprietary Instruction Set Architecture (ISA) supporting both partial and full predication and pipelined, multi-input, multi-output (MIMO) instruction extensions. The LE1 CMP is parameterizable as to the number of processors, their issue capability, internal microarchitectural features, functional unit mix and latency and the local memory system architecture.Preliminary results indicate near-linear performance improvement when executing a threaded version of the Mandelbrot calculation on 2-way and 4-way processor configurations with a 256 KB, 4-way banked tightly-coupled memory system. Similar trends are seen when executing a threaded matrix multiplication benchmark. We present these findings along with VLSI implementations of 4-way, dual-issue and 3-way, quad issue multiprocessor configurations.

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A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder

Cited by 30 publications

References 1 publication

The potential of the cell processor for scientific computing

The potential of the cell processor for scientific computing

Lightweight DMA management mechanisms for multiprocessors on FPGA

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

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