A methodology for implementing decimator FIR filters on FPGA

Harize, Saliha; Benouaret, Mohamed; Doghmane, Noureddine

doi:10.1016/j.aeue.2013.05.013

Cited by 13 publications

(11 citation statements)

References 5 publications

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“…This register value is added with multiplier output stored in the same register. Finally, the output is delivered from the register [13][14][15][16][17][18][19][20][21]. The standard form of the N-tap FIR filter is given below:…”

Section: Methodsmentioning

confidence: 99%

“…In the current techniques, radix 2-based recoding helps to design a Booth multiplier. The existing multiplier affords high complexity, highly optimized area, and low speed [13][14][15][16][17][18][19][20][21].…”

Section: Compact Booth Multipliermentioning

confidence: 99%

“…The CLA adders are implemented as a combination of 4-bit modules for designing higher-level modules. Figure 12.5 shows a detailed flowchart of the FIRF implementation for ECG signal denoising [13][14][15][16][17][18][19][20][21]. (Figs.…”

Section: Carry Look-ahead (Cla) Addermentioning

confidence: 99%

“…The Booth multiplier, constructed on a radix 4 encoding scheme, is presented in this work for low-power applications. This design arises as a good option for high-speed DSP applications, thanks to the usage of VD and CLA [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23].…”

mentioning

confidence: 99%

See 3 more Smart Citations

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

Sowmya¹,

Chandana²,

Anjana³

2020

Advances in Multidisciplinary Medical Technologies ─ Engineering, Modeling and Findings

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Finite impulse response (FIR) filter implementations abound and play a major part in signal processing applications. The FIR filter (FIRF) delivers several benefits, and there exist many different realizations, such as designs using a system generator, normal FIRF, decimator FIRF, genetic algorithm (GA)-based, and parallelbased, among others. Most architectures utilize more hardware with less efficiency. Moreover, these existing architectures did not concentrate on and explored the applications' characteristics. The FIRF affords several paybacks like (i) computational efficiency in multi-rate frameworks, (ii) manageable linear phase response, and (iii) the desirable numerical ability to accomplish finite precision and fractional arithmetic. The digital multi-standard RFIR filter is implemented in wireless applications to decrease the bit error rate (BER). The discrete FIRF can render efficient designs with low-power consumption and high performance. Earlier, hordes of research articles described different FIRF designs without handling signal denoising with an effective multiplier design. Booth's algorithm performs multiplication by multiplying two signed binary numbers in 2's complement notation. The Booth multiplier (BM) overcomes the reduced area drawback, but it would not work with alternation of zeros and ones since it entails more additions and subtractions [1-3]. This problem is overcome by the modified BM (MBM), which contains half the number of partial product rows. It functions well regarding speed and power consumption. On the other hand, its main shortcoming is sloppy work for negative numbers [4, 5].

show abstract

Section: Methodsmentioning

confidence: 99%

Section: Compact Booth Multipliermentioning

confidence: 99%

Section: Carry Look-ahead (Cla) Addermentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

Sowmya¹,

Chandana²,

Anjana³

2020

Advances in Multidisciplinary Medical Technologies ─ Engineering, Modeling and Findings

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show abstract

“…The corresponding projection matrix is given by (22). The PE index associated with a point p in the DG is given by (23). Similar to design option #1, the number of processors is finite and also two PEs are active at any given time step.…”

Section: Design Option #4: Using S 2 = [1 1] and D 1 = [1 0] Tmentioning

confidence: 99%

Decimator systolic arrays design space exploration for multirate signal processing applications

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained that combined the antialiasing filter and the downsampler. Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation and compared with the other two well known decimator designs; namely, conventional design, in which the antialiasing filter is followed by a downsampling and the polyphase design, in which a commutator is followed by the polyphase antialiasing filter. Fieldprogrammable gate array implementations for the proposed and the other two designs confirm that the proposed decimator implementation outperforms in terms of area, speed, and power as the decimation factor increases regardless of the number of FIR filter coefficients.

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Signal adaptive hardware implementation of a system for highly nonstationary two-dimensional FM signal estimation

Ivanovic

Radovic

2015

AEU - International Journal of Electronics and Communications

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A methodology for implementing decimator FIR filters on FPGA

Cited by 13 publications

References 5 publications

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

Decimator systolic arrays design space exploration for multirate signal processing applications

Signal adaptive hardware implementation of a system for highly nonstationary two-dimensional FM signal estimation

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