In this paper we develop a multiple-clock-cycle signal adaptive hardware design of an optimal nonstationary (time-varying) filtering system. The proposed design is based on the real-time results of time-frequency (TF) analysis and the estimation of instantaneous frequency (IF). It permits multiple detection of the local filter's region of support (FRS) in the observed increment of time, resulting in the efficient filtering of multicomponent frequency modulated (FM) signals. The proposed design takes a variable number of clock (CLK) cycles-the only necessary ones regarding the highest quality of IF estimation-in different TF points within the execution. In this way it allows the implemented system to optimize the computational cost, as well as the time required for execution. Further, the proposed serial design optimizes critical design performances, related to the hardware complexity, making it a suitable system for real-time implementation on an integrated chip. Also, by applying the pipelining technique, it allows overlapping between different TF points within the execution, additionally improving the time required for time-varying filtering. The design has been verified by a field-programmable gate array (FPGA) circuit design, capable of performing filtering of nonstationary FM signals in real-time.

Multiple-clock-cycle implementation (MCI) of a flexible system for time-frequency (TF) signal analysis is presented. Some very important and frequently used time-frequency distributions (TFDs) can be realized by using the proposed architecture: (i) the spectrogram (SPEC) and the pseudo-Wigner distribution (WD), as the oldest and the most important tools used in TF signal analysis; (ii) the S-method (SM) with various convolution window widths, as intensively used reduced interference TFD. This architecture is based on the short-time Fourier transformation (STFT) realization in the first clock cycle. It allows the mentioned TFDs to take different numbers of clock cycles and to share functional units within their execution. These abilities represent the major advantages of multicycle design and they help reduce both hardware complexity and cost. The designed hardware is suitable for a wide range of applications, because it allows sharing in simultaneous realizations of the higher-order TFDs. Also, it can be accommodated for the implementation of the SM with signal-dependent convolution window width. In order to verify the results on real devices, proposed architecture has been implemented with a field programmable gate array (FPGA) chips. Also, at the implementation (silicon) level, it has been compared with the single-cycle implementation (SCI) architecture.

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This paper outlines the development of a multiple-clock-cycle implementation (MCI) of a signal adaptive two-dimensional (2D) system for space/spatial-frequency (S/SF) signal analysis. The design is based on a method for improved S/SF representation of the analyzed 2D signals, also proposed here. The proposed MCI design optimizes critical design performances related to hardware complexity, making it a suitable system for real time implementation on an integrated chip. Additionally, the design allows the implemented system to take a variable number of clock cycles (CLKs) (the only necessary ones regarding desirable-2D Wigner distribution-presentation of autoterms) in different frequency-frequency points during the execution. This ability represents a major advantage of the proposed design which helps to optimize the time required for execution and produce an improved, crossterms-free S/SF signal representation. The design has been verified by a field-programmable gate array (FPGA) circuit design, capable of performing S/SF analysis of 2D signals in real time.