The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising

Abstract

Finite impulse response (FIR) filter implementations abound and play a major part in signal processing applications. The FIR filter (FIRF) delivers several benefits, and there exist many different realizations, such as designs using a system generator, normal FIRF, decimator FIRF, genetic algorithm (GA)-based, and parallelbased, among others. Most architectures utilize more hardware with less efficiency. Moreover, these existing architectures did not concentrate on and explored the applications' characteristics. The FIRF affords several paybacks like (i) computational efficiency in multi-rate frameworks, (ii) manageable linear phase response, and (iii) the desirable numerical ability to accomplish finite precision and fractional arithmetic. The digital multi-standard RFIR filter is implemented in wireless applications to decrease the bit error rate (BER). The discrete FIRF can render efficient designs with low-power consumption and high performance. Earlier, hordes of research articles described different FIRF designs without handling signal denoising with an effective multiplier design. Booth's algorithm performs multiplication by multiplying two signed binary numbers in 2's complement notation. The Booth multiplier (BM) overcomes the reduced area drawback, but it would not work with alternation of zeros and ones since it entails more additions and subtractions [1-3]. This problem is overcome by the modified BM (MBM), which contains half the number of partial product rows. It functions well regarding speed and power consumption. On the other hand, its main shortcoming is sloppy work for negative numbers [4, 5].