A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach

Oklobdzija, Vojin G.; Villeger, D.; Liu, S.S.

doi:10.1109/12.485568

Cited by 296 publications

(139 citation statements)

References 25 publications

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“…This section highlights the existence of 7:3 compressor for summation of seven partial products in parallel at the centre of compressor tree, which lead to faster multiplication process. This is due to hidden critical path of carry signal that is reduced by optimising the connection of compressor topology [14][15][16]. …”

Section: A 7:3 Compressor Architecturementioning

confidence: 99%

Speed and area analysis on hierarchy multiplier

Wong

Hussin

2017

EPJ Web Conf.

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Abstract. This paper proposes designs of hierarchy multiplier by utilising different designs on 4:2 and 7:3 compressor and multiple compressors. The hierarchy multipliers is optimised in the term of speed or area of hierarchy multiplier by redesigning 4:2 compressor units and introducing a combination of 4:2 compressor and 7:3 compressor units in a Vedic multiplier block. All designs are simulated using Altera Quartus II software. The aim of this paper is to improve the performance in speed by moderately increasing the area without considering the power consumption. The proposed design is 4.5% to 8.3% faster and consumes -0.5% to 5.8% less area.

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Section: A 7:3 Compressor Architecturementioning

confidence: 99%

Speed and area analysis on hierarchy multiplier

Wong

Hussin

2017

EPJ Web Conf.

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“…Because of the different characteristics of FA inputs, it is possible to optimize signal flow with respect to propagation delay. This technique has been applied in TDM tree multipliers [15]. In addition to delay, signal flow optimization affects power [7].…”

Section: Optimization Of Fasmentioning

confidence: 99%

“…Radix-2 and radix-4 TDM schemes [15][18] are chosen because they are the best tree multipliers to our knowledge. In addition, tree multipliers based on [4:2] and [3:2] CSAs are also used for comparison as they have more regular structures.…”

Section: Delay Comparison At Logic Levelmentioning

confidence: 99%

“…To improve regularity and compact layout, regularly structured tree (RST) with recurring blocks [6] and rectangular-styled tree by folding [8] were proposed, at the expense of more complicated interconnects. In [15], three dimensional minimization (TDM) algorithm was developed to design adders of the maximal possible size with optimized signal connections, which further shortened the PPR path by 1 ∼ 2 XOR delays. However, the resulting structure has more complex layout than a [4:2]-adder based tree.…”

Section: Introductionmentioning

confidence: 99%

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High-performance left-to-right array multiplier design

Huang¹,

Ercegovac²

16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings.

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We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed design shows equivalent performance as tree multipliers for n ≤ 32. An efficient radix-4 recoding logic generates the partial products in a left-to-right order. The partial products are split into upper and lower groups. Each group is reduced using [3:2] adders with optimized signal flows and the carry-save results from two groups are combined using a [4:2] adder. The final product is obtained with a prefix adder optimized to match the non-uniform arrival profile of the inputs. Layout experiments indicate that upper/lower split multipliers have slightly less area and power than optimized tree multipliers while keeping the same delay for n ≤ 32.

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“…The efficiency of such a structure is higher since it reduces the number of partial product bits by one half at each stage. The delay of 4:2 compressor is 3 XOR gates in series making it more efficient than using 3:2 counters (full adder) in a regular "Wallace Tree" and has important feature that the interconnections between 4:2 cells follow more regular pattern than in case of the "Wallace Tree" [17,18,25] .…”

Section: Proposed 4* 4 Reversible Gatementioning

confidence: 99%

Novel Reversible `TSG' Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU

Thapliyal¹,

Srinivas²

2005 5th International Conference on Information Communications &Amp; Signal Processing

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Abstract-In recent years, reversible logic has emerged as a promising computing paradigm having application in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper utilizes a new 4 * 4 reversible gate called TSG gate to build the components of a primitive reversible/quantum ALU. The most significant aspect of the TSG gate is that it can work singly as a reversible full adder, that is reversible full adder can now be implemented with a single gate only. A Novel reversible 4:2 compressor is also designed from the TSG gate which is later used to design a novel 8x8 reversible Wallace tree multiplier. It is proved that the adder, 4:2 compressor and multiplier architectures designed using the TSG gate are better than their counterparts available in literature, in terms of number of reversible gates and garbage outputs. This is perhaps, the first attempt to design a reversible 4:2 compressor and a reversible Wallace tree multiplier as far as existing literature and our knowledge is concerned. Thus, this paper provides an initial threshold to build more complex systems which can execute complicated operations using reversible logic.

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A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach

Cited by 296 publications

References 25 publications

Speed and area analysis on hierarchy multiplier

Speed and area analysis on hierarchy multiplier

High-performance left-to-right array multiplier design

Novel Reversible `TSG' Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU

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