Speed and area analysis on hierarchy multiplier

Wong, Moon Cheng; Hussin, Razaidi

doi:10.1051/epjconf/201716201067

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…The architecture of hierarchy multiplier for previous work is illustrated as the Figure 3 (a) [4,9] in general whereas There are three designs are implemented. For the first design, the two 4-bit BEC is used to replace 8-bit BEC only of entire architecture of hierarchical multiplier.…”

Section: Proposed Designmentioning

confidence: 99%

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Power-Effective Vedic-Hierarchical Multiplier

Cheng,

Arshad

2020

IJIE

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The motivation of this project is to design a power effective multiplier without having much drawback in term of time constraint and area utilization. This is due to the overall power dissipation which increases in direct proportion to the increase in power density. The area and time constraint are considered as pertinent design parameters with the increase in market demand for high performance and complex portable systems. The current hierarchical multiplier designs suffer on long critical path and large area utilization. These parameters caused the hierarchical multiplier design to be less effective in term of power saving. The objective of this research is to reduce overall power dissipation and ensure that the multiplierachieve timing requirement. This paper proposes the design 1 by using two 4-bit Binary-to-Excess-One Converter (BEC) instead of an 8-bit BEC. The BEC reduce the critical path and cause low power dissipation. Design 2 which is implementation of Carry Select Adder (CSlA) with tristate buffer is to reduce logic elements. The power dissipation is reduced because of the decrease in the number of logic elements which leads to the lower number of logic gates. Both advantages of design 1 and design 2 are combined to become design 3. Design 3 is the lowest power dissipation design because it consists of the lowest number of logic elements and the shortest critical path. The timing requirement for all designs are met as shown by the positive slack time of 9.034 ns, 8.686 ns and 9.404 ns respectively. The power dissipation of the combinational multipliers designs have been improved to 60.96%, 60.89% and 61.02% respectively.

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Section: Proposed Designmentioning

confidence: 99%

“…The proposed CSlA in Figure 4 will use tri-sate buffer to replace MUX from the conventional CSlA [4,9,10]. The unused input will cut off by tristate buffer to save logic element and power instead of conventional MUX [11].…”

Section: Carry Select Adder (Csla)mentioning

confidence: 99%

Power-Effective Vedic-Hierarchical Multiplier

Cheng,

Arshad

2020

IJIE

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16×16 fast signed multiplier using Booth and Vedic architecture

Shing¹,

Hussin²,

Kamarudin³

et al. 2018

AIP Conference Proceedings

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Design and Analysis of 32-Bit Signed and Unsigned Multiplier Using Booth, Vedic and Wallace Architecture

Yong

Hussin

Kamarudin

et al. 2021

J. Phys.: Conf. Ser.

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This paper presents the implementation and performance comparison of the Booth encoding technique and Wallace Tree reduction scheme on Vedic architecture. The radix-4 Booth encoder is widely used to enhance the multiplication speed as it has the capability to reduce the number of partial products generated by half. Vedic multiplier partitions the inputs into two blocks to speed up the partial product generation and Wallace Tree reduction scheme speed up the partial product addition process by eliminating the carry chain of the addition. Radix-4 Booth encoding scheme Vedic multiplier with and without Wallace Tree partial product reduction scheme for signed and unsigned multiplication was designed and synthesized in Synopsys 130 nm technology. For unsigned multiplier, the Booth-Vedic multiplier is 37.29% faster and 26.13% smaller while the Booth-Vedic-Wallace multiplier is 39.79% faster and 28.81% smaller when compared with Vedic multiplier. The performance of both multipliers was dropped when used in signed multiplication due to signed extension during the partial product addition process. All the multiplier is functionally verified using modified testbench that is based on the concept of UVM testbench.

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Speed and area analysis on hierarchy multiplier

Cited by 3 publications

References 11 publications

Power-Effective Vedic-Hierarchical Multiplier

Power-Effective Vedic-Hierarchical Multiplier

16×16 fast signed multiplier using Booth and Vedic architecture

Design and Analysis of 32-Bit Signed and Unsigned Multiplier Using Booth, Vedic and Wallace Architecture

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