A Majority-Logic Nanodevice Using a Balanced Pair of Single-Electron Boxes

Oya, Takahide; Asai, Tetsuya; Fukui, Takashi; Amemiya, Yoshihito

doi:10.1166/jnn.2002.108

Cited by 39 publications

(37 citation statements)

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“…( ) By setting one of the three inputs of the minority gate as a logic 0 or 1, the gate implements a two-input logic NAND or two-input logic NOR gate, respectively [8]. The obtained functions are given by ( ) ( ) …”

Section: Single Electron Tunneling Technologymentioning

confidence: 99%

A Comparative Study of Majority/Minority Logic Circuit Synthesis Methods for Post-CMOS Nanotechnologies

Almatrood¹,

Singh²

2017

ENG

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The physical limitations of complementary metal-oxide semiconductor (CMOS) technology have led many researchers to consider other alternative technologies. Quantum-dot cellular automate (QCA), single electron tunneling (SET), tunneling phase logic (TPL), spintronic devices, etc., are some of the nanotechnologies that are being considered as possible replacements for CMOS. In these nanotechnologies, the basic logic units used to implement circuits are majority and/or minority gates. Several majority/minority logic circuit synthesis methods have been proposed. In this paper, we give a comparative study of the existing majority/minority logic circuit synthesis methods that are capable of synthesizing multi-input multi-output Boolean functions. Each of these methods is discussed in detail. The optimization priorities given to different factors such as gates, levels, inverters, etc., vary with technologies. Based on these optimization factors, the results obtained from different synthesis methods are compared. The paper also analyzes the optimization capabilities of different methods and discusses directions for future research in the synthesis of majority/minority logic networks.

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Section: Single Electron Tunneling Technologymentioning

confidence: 99%

A Comparative Study of Majority/Minority Logic Circuit Synthesis Methods for Post-CMOS Nanotechnologies

Almatrood¹,

Singh²

2017

ENG

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“…By forcing one of the three inputs to logic 0 or 1, "NAND" gate and "NOR" gate are obtained for SET minority gate, while "AND" gate and NOR gate are obtained for SET majority gate [6]. …”

Section: Set Technologymentioning

confidence: 99%

“…For example, as gate lengths are reduced below 10 nm, quantum effects are likely to dominate the performance of the device, resulting in increased gate leakage current, capacitive coupling, electro-migration failures, doping fluctuations and increased difficulties in lithography [1]. Alternative technologies such as Quantum-dot Cellular Automata (QCA) [2][3][4][5], Single Electron Tunneling (SET) [6,7] and Tunneling Phase Logic (TPL) [8] are being considered as possible replacements for CMOS. Unlike CMOS technology which uses "NAND/NOR/NOT" gates to implement circuits, QCA uses majority logic, SET uses both majority and minority logic, and TPL uses minority logic.…”

Section: Introductionmentioning

confidence: 99%

Synthesis of Majority/Minority Logic Networks

Wang

Niamat

Vemuru

et al. 2015

IEEE Trans. Nanotechnology

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As CMOS technology reaches its physical limits, new technologies such as Quantum-dot Cellular Automata (QCA), Single Electron Tunneling (SET) and Tunneling Phase Logic (TPL) are being proposed as alternatives to CMOS technology. These technologies use either majority or minority logic to implement logic functions. Existing majority/minority logic synthesis methods, based on three-feasible networks, often result in sub-optimal solutions. In this paper, an efficient algorithm to find the minimal majority gate mapping, along with a Majority expression Look-Up Table (MLUT) is developed. Based on the MLUT, a comprehensive majority/minority logic synthesis technique is proposed. A redundancy removal method is also developed to further optimize the synthesized circuit. This technique makes effort towards achieving different optimization goals and results in fewer majority gates and fewer levels than previous methods. For the 29 MCNC benchmark circuits, when targeted to optimize the logic levels, there is an average reduction of 7.0% in the number of levels as well as 6.3% in the number of gates. For optimization targeted to reduce gate counts, there is an average reduction of 9.5% in the number of gates as well as 0.8% in the number of levels, as compared to the best available method.Index Terms -logic synthesis, majority gates, quantum-dot cellular automata (QCA) 

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“…One of us previously presented and demonstrated a process technology that can be used to fabricate such an array structure [6]. This technology uses self-organized crystal growth based on selective-area metalorganic vapor-phase epitaxy (see [7] for this epitaxy method).…”

Section: Toward Actual Devicesmentioning

confidence: 99%

A photon position sensor consisting of single-electron circuits

2009

Self Cite

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Abstract. This paper proposes a solid-state sensor that can detect the position of incident photons with a high spatial resolution. The sensor consists of a twodimensional array of single-electron oscillators, each coupled to its neighbors through coupling capacitors. An incident photon triggers an excitatory circular wave of electron tunneling in the oscillator array. The wave propagates in all directions to reach the periphery of the array. By measuring the arrival time of the wave at the periphery, we can know the position of the incident photon. Tunneling wave's generation, propagation, arrival at the array periphery, and the determination of incident photon positions are demonstrated with the results of Monte-Carlo based computer simulations.

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A Majority-Logic Nanodevice Using a Balanced Pair of Single-Electron Boxes

Cited by 39 publications

References 0 publications

A Comparative Study of Majority/Minority Logic Circuit Synthesis Methods for Post-CMOS Nanotechnologies

A Comparative Study of Majority/Minority Logic Circuit Synthesis Methods for Post-CMOS Nanotechnologies

Synthesis of Majority/Minority Logic Networks

A photon position sensor consisting of single-electron circuits

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