A low voltage 8-T SRAM with PVT-tracking bitline sensing margin enhancement for high operating temperature (up to 300&amp;#x00B0;C)

Kim, Tony T.; Ba, Ngoc Le

doi:10.1109/asscc.2013.6691025

Cited by 5 publications

(2 citation statements)

References 11 publications

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“…In addition, to minimize the performance variations caused by the wide operating temperature change, we adopted near-threshold operation where the overall variation in device current is minimized due to the complementary effect of temperature on mobility and threshold voltage. A part of this paper has been presented in [31]. In this paper, we present more comprehensive analysis at high temperature and the detailed operation of the proposed technique with additional measurement results.…”

Section: Introductionmentioning

confidence: 99%

Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C

Kim

2014

IEEE J. Solid-State Circuits

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This paper presents an 8-Kbit low power SRAM for high temperature (up to 300C) applications. For reliable low voltage operation, we employed a decoupled 8T SRAM cell structure. To minimize the performance variations caused by the wide operating temperate range, supply voltage is selected in the near-threshold region. A temperature-aware bitline sensing margin enhancement technique is proposed to mitigate the impact of significantly increased bitline leakage on bitline swing and sensing window. A temperature-tracking control circuit generates bias voltage for optimal pull-up current for realizing the proposed enhancement technique. Test chips were fabricated in a commercial 5 V, 1.0-µm SOI technology. Test chip measurement demonstrates successful operation down to 2 V at 300C. The average energy of 0.94 pJ was achieved at 2 V and 300C.

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Section: Introductionmentioning

confidence: 99%

Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C

Kim

2014

IEEE J. Solid-State Circuits

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“…Conventional sensing scheme based upon dynamic operation (precharge and conditional discharge) is highly likely to fail to provide acceptable sensing margin. To address this, Static Read Bitline (S-RBL) was proposed in[6] whose principle is illustrated in During read operation, a read word line (RWL<O» is activated like the conventional decoupled SRAMs. However, the PMOS devices (Ml, M2, M3, and M4) provide pull-up reference current (Ire!)…”

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confidence: 99%

Low power memory design for high temperature in ruggedized electronics

Kim

Tuan

et al. 2014

2014 International SoC Design Conference (ISOCC)

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Applications such as Logging-While-Drilling (L WD), automotive, and aerospace systems require electronics whose operating temperature is much higher than that of conventional consumer electronics. One of the most critical functional blocks for high temperature operation is memory due to the significantly increased leakage. This paper explains two different memories (SRAM and NEMS NVM) for high temperature operation. In the SRAM, circuit techniques for improving sensing margin under the leaky bit line condition will be discussed. In the NEM NVM, two adhesion-force-based NEM NYM devices will be introduced.

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