A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

Luo, Xiaorong; Luo, Yong; Fan, Ye; Hu, Grace; Wang, Xiaowei; Zhang, Zhengyuan; Yang, Fan; Cai, Jin-Yong; Wang, Pei; Zhou, Kun

doi:10.1088/1674-1056/22/2/027304

Cited by 3 publications

(1 citation statement)

References 9 publications

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“…double /triple RESURF) narrows the current path in the N-drift region and induces a JFET region in the on-state, and thus restricts the decrease of the R on.sp . [6][7][8][9] The REBULF technology enhances BV by introducing an N-type buried layer in the P-substrate to redistribute the E-field on the source side and the drain side. [10][11][12] Though the VLD in the drift region can achieve a high BV , the low doping on the source side leads to a 'hotspot' [13][14][15] and easily causes a thermal breakdown.…”

Section: Introductionmentioning

confidence: 99%

A novel LDMOS with a junction field plate and a partial N-buried layer

et al. 2014

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Section: Introductionmentioning

confidence: 99%

A novel LDMOS with a junction field plate and a partial N-buried layer

et al. 2014

Self Cite

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Models on threshold voltage/subthreshold swing and structural design of high-k gate dielectric GeOI MOSFET

Min-Min¹,

Xu²,

Lu³

et al. 2014

Acta Phys. Sin.

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An analytical model on threshold voltage and subthreshold swing for high-k gate dielectric GeOI MOSFET (metal-oxide-semiconductor field-effect transistor) is established by considering the two-dimensional effects in both channel and buried-oxide layers and solving two-dimensional Poisson’s equation. The influences of the main structural parameters of the device on threshold voltage and subthreshold swing, and the short-channel effects, drain induction barrier lower effect and substrate-biased effect are investigated using the model, and the design principles and value range of the structural parameters are presented to optimize the electrical performances of the device. The simulated results are in good agreement with the TCAD simulated data, confirming the validity of the model.

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A dual-trench silicon on insulator high voltage device with an L-shaped source field plate

Shi¹,

Liu²,

Yao³

et al. 2014

Acta Phys. Sin.

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To improve the breakdown voltage and reduce the specific on-resistance of a small size silicon on insulator (SOI) device, a dual-trench SOI high voltage device with an L-shaped source field plate is proposed. The device has the features as follows: first, a trench gate is adopted. The trench gate widens the current conduction area and makes the current conduction path shorter, thus lowering the specific on-resistance. Second, a SiO2 dielectric layer is introduced into the drift region. This dielectric layer can hold a high electric field, which makes the breakdown voltage greatly increased. Third, an L-shaped source field plate is introduced. This field plate modulates the electric field in the drift region, so increases the optimized doping concentration of the drift region significantly and reduces the specific on-resistance. The results from the two-dimensional semiconductor simulator show that as compared with a conventional SOI device at the same cell pitch, the breakdown voltage is increased by 151%, and the specific on-resistance is reduced by 20%. The specific on-resistance is reduced by 80% at the same breakdown voltage. Compared with a dual-trench SOI device with the same cell pitch, the proposed device maintains the same high breakdown voltage as the dual- trench SOI device, and at the same time, the specific on-resistance is decreased by 26%.

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A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

Cited by 3 publications

References 9 publications

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel LDMOS with a junction field plate and a partial N-buried layer

Models on threshold voltage/subthreshold swing and structural design of high-k gate dielectric GeOI MOSFET

A dual-trench silicon on insulator high voltage device with an L-shaped source field plate

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