A novel LDMOS with a junction field plate and a partial N-buried layer

Shi, Xianlong; Luo, Xiaorong; Wei, Jie; Tan, Qiao; Liu, Jianping; Xu, Qing; Li, Pengcheng; Ruichao, Tian; Ma, Dongling

doi:10.1088/1674-1056/23/12/127303

Cited by 2 publications

(1 citation statement)

References 12 publications

(15 reference statements)

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“…[1][2][3][4][5][6] The dielectric trench in the drift region of LDMOS devices is adopted as an effective technique to enhance breakdown voltage and reduce specific on-resistance R on,sp . [7][8][9][10][11] State-of-theart LDMOS devices obtained by the dielectric trench to sustain a high reversed voltage have been reported. [12][13][14][15][16][17] In these devices, breakdown occurs in the drift region for the crowded electric field.…”

Section: Introductionmentioning

confidence: 99%

Modeling electric field of power metal-oxide-semiconductor field-effect transistor with dielectric trench based on Schwarz–Christoffel transformation*

Wang¹,

Liao²,

Wang³

2019

Chinese Phys. B

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A power metal-oxide-semiconductor field-effect transistor (MOSFET) with dielectric trench is investigated to enhance the reversed blocking capability. The dielectric trench with a low permittivity to reduce the electric field at reversed blocking state has been studied. To analyze the electric field, the drift region is segmented into four regions, where the conformal mapping method based on Schwarz–Christoffel transformation has been applied. According to the analysis, the improvement in the electric field for using the low permittivity trench is mainly due to the two electric field peaks generated in the drift region around this dielectric trench. The analytical results of the electric field and the potential models are in good agreement with the simulation results.

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Section: Introductionmentioning

confidence: 99%

Modeling electric field of power metal-oxide-semiconductor field-effect transistor with dielectric trench based on Schwarz–Christoffel transformation*

Wang¹,

Liao²,

Wang³

2019

Chinese Phys. B

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Investigation of SiC trench MOSFET with floating islands

Song

Tang

Zhang

et al. 2016

IET Power Electronics

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The silicon carbide trench metal-oxide-semiconductor field-effect transistors (SiC UMOSFET) with P + floating island (FLI) which shields the gate oxide at the bottom of the gate trench from the high electric field during the blocking state and enhances the breakdown voltage (BV), is presented in this study using two-dimensional simulations. The effects of doping concentration, length and position of FLI on BV, electric field distribution and specific on-resistance (R on,sp) are studied, thereby providing particularly useful guidelines for the design of this new type of device when considering the breakdown of the gate oxide layer. For the suitable device design, the results indicate that BV and Baliga figure of merit are, respectively, increased by 150 and 439% compared with a conventional SiC UMOSFET. At the same time, the SiC FLI UMOSFET has smaller gate-drain capacitance and better switching performance compared with the conventional UMOSFET on the condition of the same drift layer parameters. FLI introduced have almost no influence on the recovery characteristics of body diode.

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A novel LDMOS with a junction field plate and a partial N-buried layer

Cited by 2 publications

References 12 publications

Modeling electric field of power metal-oxide-semiconductor field-effect transistor with dielectric trench based on Schwarz–Christoffel transformation*

Modeling electric field of power metal-oxide-semiconductor field-effect transistor with dielectric trench based on Schwarz–Christoffel transformation*

Investigation of SiC trench MOSFET with floating islands

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