A low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuit

Abstract

An asynchronous pipeline scheme that combines a low power static circuit with a high-speed dual-rail dynamic circuit is proposed. The scheme utilizes a dual-rail circuit only in the critical path of an SRT division and square root calculation unit. The proposed implementation of the calculation unit reduced power consumption by more than 112 of the full-dynamic implementation while maintaining the calculation speed. Because of the elimination of spurious transitions, the proposed implementation showed even less power consumption over synchronous static circuit implementations. By using 0.3 , U m triple metal CMOS technology, the calculation time of floating point 56-b full mantissa division and square root is expected to be 45ns in the worst case.

Low power self-timed Radix-2 division (poster session)

“…The dynamic operation and dual-rail signaling for self-timing not only double the connecting wires and silicon area but also increase the power consumption. To resolve these problems, a method to combine single-rail static circuits with dual-rail dynamic circuits for self-timed operation has been reported in [4]. As a result, power consumption for division is significantly reduced, but its performance is degraded due to being unable to exploit the performance enhancement technique in [1].…”

Practical advances in asynchronous design and in asynchronous/synchronous interfaces

“…Consequently, this technique has been applied to other academic and industrial designs, such as a division and square root unit design by Matsubara and Ide [45], a self-timed packet switch design by Yun et al [78], and a Huffman decoder design by Benes et al [3]. There have been other iterative structure designs that achieve high performance with data-dependent computation times, such as a bundled data multiplier design by Kearney and Bergmann [34].…”

<title>On digit-recurrence division algorithms for self-timed circuits</title>

“…But in the case of the division operation, only straightforward algorithms have been studied. Most of the previous works use a radix-2 SRT algorithm (with quotient digits in ¢ ¡ ¤ £ ¦ ¥ § © ¥ £ ) and a residual represented using a carry-save number system [10,11,12,13] or a borrow-save number system [14]. A recent high-radix approach [15] presents a speculative radix-64 or radix-128 SRT algorithm.…”