We show that an efficient implementation of a selftimed statistical carry lookahead adder can be built from a Manchester carry chain. By exploiting multiple-output DCVSL, the presented implementation not only relieve the delay matching problem of previous design in completion detection but also reduce the number of transistors. The worst case delay is comparable to the previous design, and 25.8% of average power consumption is reduced.
A self-timed radix-2 division scheme for low power consumption is proposed. By replacing dual-rail dynamic circuits in non-critical data paths with single-rail static circuits, power dissipation is decreased, yet performance is maintained by speculative remainder computation. SPICE simulation results show that the proposed design can achieve 33.8-ns latency for 56-bit mantissa division and 47% energy reduction compared to a fully dual-rail version.
A self-timed radix-2 division scheme for low power consumption is proposed. By replacing dual-rail dynamic circuits in non-critical data paths with single-rail static circuits, power dissipation is decreased, yet performance is maintained by speculative remainder computation. SPICE simulation results show that the proposed design can achieve 33.8-11s latency for 56-bit mantissa division and 47% energy reduction compared to a fully dual-rail version.
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