A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter

Yamasaki, Tokiwa; Nakayama, Tetsuo; Shibata, Tadashi

doi:10.1016/j.vlsi.2008.09.002

Cited by 1 publication

(2 citation statements)

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“…Liau and Chiueh utilized the pre-filter for power minimization by reducing the number of additions [7]. A low-power switched-current matched filter for CDMA systems was developed by Yamasaki et al which eliminated the front-end voltage-to-current converter [11]. Design of parallel matched filter by applying two step correlation algorithm in data processing was proposed to reduce calculation cost by Tsugawara and Miyanaga [9].…”

Section: Introductionmentioning

confidence: 99%

“…A new algorithm of digital matched filter with a segment processing method was proposed to reduce the computation complexity by Guan and Chen [10]. A low-power switched-current matched filter for CDMA systems was developed by Yamasaki et al which eliminated the front-end voltage-to-current converter [11]. However, none of the design could avoid the adder circuit and numerous multiplications.…”

Section: Introductionmentioning

confidence: 99%

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Design of a novel adder‐less Barker matched filter for RFID

Amin

Reaz

Jalil

2013

Circuit Theory & Apps

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Radio frequency identification (RFID) is the utilization of the radio frequency for the purpose of identification. RFID is lagging behind due to vendor specific solutions and excessive implementation cost. A Wireless Fidelity (WiFi) compatible IEEE 802.11 RFID tag can overcome these limitations. IEEE 802.11 utilizes Direct Sequence Spread Spectrum (DSSS) technique and a matched filter is a vital block in a DSSS system. A low-power and low-area novel adder-less Barker matched filter is proposed in this paper by eliminating the conventional multiple multiplications. The matched filter designed in 0.18 mm CMOS technology achieves average and maximum power consumption of 33.747 mW and 8.08 mW, respectively and chip area of 0.41184 mm 2 only. The simulation result shows the correct matching of data against the threshold value. Compared with the conventional matched filter, the design achieves 25% power reduction (maximum power) and 51% chip area reduction. Therefore, the design will help to implement a low-power matched filter for IEEE 801.11 compatible RFID tag.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%