A low-power self-timed Viterbi decoder

Abstract

Viterbi decoders are used for decoding data encoded using convolutional forward error correction codes or data that suffers from inter-symbol interference. They occur in a large proportion of digital transmission and digital recording systems, including digital mobile telephony and digital TV broadcast, CD-ROM and magnetic disk reading. This paper describes a design for a selftimed Viterbi decoder. The new design is based upon serial, unary arithmetic for the manipulation and storage of metrics. In the trace-back system, multiple concurrent trace-backs may be running and trace-backs are terminated as soon as they cease to be useful. The new architecture occupies between 29% and 23% less area than a selection of synchronous implementations with the same design parameters which use the same process and cell-library.

No-Handshake Asynchronous Survivor Memory Unit for a Viterbi Decoder

“…The resulting output bit error rate (BER) and averaged power consumptions for different signal to noise ratios of code rate 1/2 and is given in Table II. The throughput is 45Mbit/sec in these simulations which is equal to the targeted throughput of the reference designs in [1] and [6]. It can be seen that the power increases only relatively slowly with increasing input BER.…”

“…This suggests that trace backs in the new SMU consume only a small portion of the overall SMU power. The average power consumption and area of this new SMU design is compared in Table III with low power Viterbi decoder designs from [6] and [1], which are implemented with singleended pass-transistor logic (SPL) and asynchronous logic respectively. Since the SPL design is implemented with the .35 micron CMOS technology and a 3.3V supply voltage, its power and area are scaled down by factors of 8 and 4 respectively.…”

“…On the contrary to a synchronised design [1], the timing is individually scheduled in an asynchronous system and multiple trace backs are performed concurrently and continuously controlled by handshakes. However the major implementation issue of the asynchronous design is the overhead of handshake logic that consumes extra power.…”

“…A Viterbi decoder normally comprises three blocks [1] as shown in Figure 4. The Branch Metric Unit (BMU) computes the branch metrics of the input symbols.…”

“…In these systems convolution codes can be used to encode the data stream into a longer stream carrying redundant information. The Viterbi decoder is then used to decode the received data and eliminate errors caused by the noise and reconstruct the original signal [1].…”