Abstract:Abstract-The Survivor Memory Unit (SMU) is a vital part of a Viterbi decoder design. So far, classical implementations of SMU employ the register exchange or the trace back approaches. In the conventional trace back implementation, a read-write RAM architecture is generally adopted which requires a large size of memory. This gives the SMU design both area and power overhead. This paper presents a new no-handshake asynchronous approach to implement the trace back method. The SMU design based on this new archite… Show more
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