Synthesis of Asynchronous Hardware from Petri Nets

Carmona, Josep; Cortadella, Jordi; Khomenko, Victor; Yakovlev, A. V.

doi:10.1007/978-3-540-27755-2_9

Cited by 9 publications

(4 citation statements)

References 57 publications

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“…For instance, targeting choice-free Petri nets, 4 i.e., finding whether a given specification can be implemented choice-freely, has some interesting practical motivations. Such nets are wellliked in hardware design and synthesis circles [6], since they exclude hazards as well as race conditions [7] and complete state coding conflicts [8]. Also, full distributability in the sense of [9] is guaranteed for them.…”

Section: Introductionmentioning

confidence: 99%

Target-oriented Petri Net Synthesis

Best

Devillers

Erofeev

et al. 2020

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When a Petri net is synthesised from a labelled transition system, it is frequently desirable that certain additional constraints are fulfilled. For example, in circuit design, one is often interested in constructing safe Petri nets. Targeting such subclasses of Petri nets is not necessarily computationally more efficient than targeting the whole class. For example, targeting safe nets is known to be NP-complete while targeting the full class of place/transition nets is polynomial, in the size of the transition system. In this paper, several classes of Petri nets are examined, and their suitability for being targeted through efficient synthesis from labelled transition systems is studied and assessed. The focus is on choice-free Petri nets and some of their subclasses. It is described how they can be synthesised efficiently from persistent transition systems, summarising and streamlining in tutorial style some of the authors’ and their groups’ work over the past few years.

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Section: Introductionmentioning

confidence: 99%

Target-oriented Petri Net Synthesis

Best

Devillers

Erofeev

et al. 2020

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“…A Petri net system is persistent if, from each reachable marking, no transition firing can disable any other transition. Persistence [7,8] is generally required when designing asynchronous hardware, notably to implement Signal Transition Graphs (STGs)-specially interpreted Petri nets-specifications as speed-independent circuits, ensuring the absence of hazards [9,10], as well as to arbiter-free synchronization of processes [11]. This property also appears in several workflow models [12].…”

Section: Introductionmentioning

confidence: 99%

On the Petri Nets with a Single Shared Place and Beyond

Hujsa¹,

Berthomieu²,

Zilio³

et al. 2020

Preprint

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Petri nets proved useful to describe various real-world systems, but many of their properties are very hard to check. To alleviate this difficulty, subclasses are often considered. The class of weighted marked graphs with relaxed place constraint (WMG ≤ for short), in which each place has at most one input and one output, and the larger class of choice-free (CF) nets, in which each place has at most one output, have been extensively studied to this end, with various applications.

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“…• Indirect translation of the model, e.g. the CONPAR language [14], a rule-based decision system [15], or the Signal-Transition-Graph approach [24]. • Breaking-down of the model into basic PN structural blocks composed of one place and one transition, each block being implemented in a configurable logic block (CLB) of the FPGA [16].…”

Section: Introductionmentioning

confidence: 99%

Petri Net Based Rapid Prototyping of Digital Complex System

Andreu

Souquet²,

Gil³

2008

2008 IEEE Computer Society Annual Symposium on VLSI

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This paper deals with the automatic translation of interpreted generalized Petri Nets with time into VHDL, for rapid prototyping on programmable logic device purposes. This approach is based on the component orientation of the VHDL language, and defines two elementary VHDL components: the place and the transition. This transition component is a "pivot" element of the approach, since it supports all the interconnections between places and transitions (i.e. it allows the structure of the PN to be built). Moreover, with the aim to reduce power consumption, we proposed to control the VHDL component's activity according to an approach based on the "activity propagation" principle since PNs are oriented graphs.

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Synthesis of Asynchronous Hardware from Petri Nets

Cited by 9 publications

References 57 publications

Target-oriented Petri Net Synthesis

Target-oriented Petri Net Synthesis

On the Petri Nets with a Single Shared Place and Beyond

Petri Net Based Rapid Prototyping of Digital Complex System

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