Petri Net Based Rapid Prototyping of Digital Complex System

Abstract

This paper deals with the automatic translation of interpreted generalized Petri Nets with time into VHDL, for rapid prototyping on programmable logic device purposes. This approach is based on the component orientation of the VHDL language, and defines two elementary VHDL components: the place and the transition. This transition component is a "pivot" element of the approach, since it supports all the interconnections between places and transitions (i.e. it allows the structure of the PN to be built). Moreover, with the aim to reduce power consumption, we proposed to control the VHDL component's activity according to an approach based on the "activity propagation" principle since PNs are oriented graphs.

Formal Validation of a Deterministic MAC Protocol

“…This problem is resolved in our context as the STIMAP model has been implemented on a FPGA based prototype using an automatic VHDL code generator named HILECOP [Andreu et al 2008]. HILECOP allows the automatic translation of Petri Nets into VHDL components.…”

“…Experiments, performed both on Ethernet based platform and on RF one [Andreu et al 2008], showed that some hardware architectures can imply important variations between the different RTT durations, but most of all these experimental measurements proved that it is possible to have significant differences between the transmission duration from the master to a DSU named T R DSUi and the one from this DSU to the master named T E DSUi . This means that the system is not a perfect one and that the hypothesis on the synchronization of the DSUs must be reconsidered: a system is neither a perfect nor a symmetric one.…”

Automatic Handling of Conflicts in Synchronous Interpreted Time Petri Nets Implementation

“…To do so, instead of dealing with all transitions at the same time, the decision of firing transitions is taken one transition after each other, beginning with the highest priority transition. A virtual marking is defined for each concerned place and initialized to the marking on the falling edge 3 . When the decision of firing a transition is taken, the virtual marking of its places is modified according to the weight of the given arcs.…”

“…It gives designers a way to decompose complex digital architectures, but also a way to formally define their behaviors. The model is then automatically transformed in a VHDL code [3]. This VHDL code can then be implemented on FPGA thanks to a tool provided by the manufacturer.…”

Control Interpreted Petri Nets - Model Checking and Synthesis

“…It can be simulated and synthesized. Synthesis is performed in form of rapid prototyping [5], what in modern methodology for digital circuits design allows for frequent verification (simulation, analysis) of developed system. Its main goal is to check, whether designed system works at all, but the circuit might be not optimized.…”