A Low Power Reconfigurable Encoder for Flash ADCs

Varghese, George Tom; Mahapatra, Kamalakanta

doi:10.1016/j.protcy.2016.08.147

Cited by 9 publications

(4 citation statements)

References 5 publications

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“…Dynamic powerdissipation and leakage power dissipation are 3.42 mW and 5.55 nW, respectively.The comparison of Fat‐Tree encoder with other encoders is presented inTable 7. It can be concluded thatFat‐Tree encoder is faster than MUX based encoder but consumes more power [2, 11, 16, 18]. A modified form of Fat‐Tree encoder is discussed inSection 3.3 exhibiting better performance

\begin{matrix} right leftthickmathspace.5em \\ T_{FATencoder} \\ = n \times \{2^{n - 1} \times INVERTER \\ + (2^{n - 1} - 1 + 2^{n - 2} {false\sum}_{i = 0}^{n - 3} (\frac{1}{2^{2 i}})) \times NAND gate \\ + (2^{n - 3} {false\sum}_{i = 0}^{n - 4} (\frac{1}{2^{2 i}})) \times NOR gate\} \\ - \{[3 \times (1 + 4 \times {false\sum}_{i = 1}^{n - 3} i) + {(2}^{n - 1} - 2) - (n - 2) \\ \times NAND gate] + {false\sum}_{i = 1}^{n - 3} i \times NOR gate\} \\ = 32 \times INVERTER + 48 \times NAND gate \\ + 8 \times NOR gate - 19 \times NAND gate \end{matrix}

…”

Section: ‐Bit Encodermentioning

confidence: 99%

“…The thermometer code is the output of the comparators and is converted to binary code by a binary encoder. Several encoders [7–13] are described in the literature, in which Fat‐Tree encoder [14] exhibits better results as compared to others. For the design of encoders, complementary logic (CML) [15] based gates are efficient in terms of noise but power consumption is more due to extra biasing circuits.…”

Section: Introductionmentioning

confidence: 99%

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Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Hussain

Kumar

Trivedi

2020

IET Circuits, Devices & Systems

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The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat-Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power-delay product of 3.335 fJ, energy-delay product of 127.7305 Js and an intrinsic area of 4.753 mm 2 .

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\begin{matrix} right leftthickmathspace.5em \\ T_{FATencoder} \\ = n \times \{2^{n - 1} \times INVERTER \\ + (2^{n - 1} - 1 + 2^{n - 2} {false\sum}_{i = 0}^{n - 3} (\frac{1}{2^{2 i}})) \times NAND gate \\ + (2^{n - 3} {false\sum}_{i = 0}^{n - 4} (\frac{1}{2^{2 i}})) \times NOR gate\} \\ - \{[3 \times (1 + 4 \times {false\sum}_{i = 1}^{n - 3} i) + {(2}^{n - 1} - 2) - (n - 2) \\ \times NAND gate] + {false\sum}_{i = 1}^{n - 3} i \times NOR gate\} \\ = 32 \times INVERTER + 48 \times NAND gate \\ + 8 \times NOR gate - 19 \times NAND gate \end{matrix}

…”

Section: ‐Bit Encodermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Hussain

Kumar

Trivedi

2020

IET Circuits, Devices & Systems

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“…Various types of ADC architecture have respective advantages and drawbacks. Flash ADCs are the fastest one among these designs because of its simple paralleled structure [3], at a cost of area and power consumption by a huge number of comparators. Because of the huge quantity of comparators, the overall function of flash ADC is largely determined by the performance of comparators.…”

Section: Introductionmentioning

confidence: 99%

Comparison of Low Power High Speed Comparator for Flash ADC

Zheng¹

2023

HSET

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The analog to digital converter (ADC), a bridge between digital world and analog world, plays a crucial role in the modern semiconductor industry. Among different types of ADCs, the flash ADC (also known as the direct-conversion ADC) is exceedingly fast, whose high sample rate enables many large bandwidth applications, such as optical communication, radar detection. The comparator circuit is one of the critical components of flash ADC. The characteristics, like latency, gain and power consumption, of comparators determine the overall performance of flash ADCs. This paper analyzes and compares different types of comparator architecture and suggests a high-performance design for flash ADC.

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“…Burada yapılan Nyquist A/S dönüştürücü sınıflandırmasına göre de yapıları yüksek hızlı ve tümüyle paralel(flash), katlama ve ara-değerleme(folding-interpolating) ve boru tipi(pipeline) A/S dönüştürücü olarak sınıflandırabiliriz. Özellikle geniş band haberleşme(mobil, kablolu, kablosuz) sistemlerinde, yazılım radyo sistemlerinin sinyal işleme uygulamalarında ve geniş band alıcı-verici sistemlerinde çoğunlukla düşük çözünürlüklü ve yüksek hızlı analog-sayısal dönüştürücüler kullanılmaktadır [3][4][5][6]. Özellikle düşük gecikme süresi ve yüksek örnekleme hızına ihtiyaç duyan sistemler için gerekli olan bir yapıdır [7].…”

Section: Gi̇ri̇ş (Introduction)unclassified

Darlington CMOS İnverter Tabanlı Paralel Analog-Sayısal Dönüştürücü Tasarımı

Aytar¹

2018

Gazi Üniversitesi Fen Bilimleri Dergisi Part C: Tasarım Ve Teknoloji

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Yapılan bu çalışmada, CMOS eşik gerilimine göre çalışan Darlington CMOS İnverter devresi kullanılarak 4-bit paralel analog-sayısal dönüştürücü(A/S) yapısı önerilmiştir. Bu yüzden genel blok yapıda kullanılan nicemleme gerilimlerini elde etmek için gerekli olan direnç bölme dizisine ihtiyaç kalmamıştır. Darlington yapısı, genellikle bipolar transistor için kullanılan bir yapı iken burada CMOS yapısı için önerilmiştir. Bu sayede kullanılan inverter devresinin kazancı artırılmıştır. Önerilen 4-bit paralel A/S dönüştürücü için besleme gerilimi +1.8V, sistemin saat frekansı 10GHz, analog giriş işaretinin frekansı 100MHz alındığında elde edilen benzetim sonuçlarına göre güç tüketimi 96.6mW, INL hatası (0/-1.24)LSB, DNL hatası ise (-0.71/+0.82)LSB olarak ölçülmüştür. Tasarımı yapılan sistemin benzetim sonuçları şematik devre üzerinden alınmıştır

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A Low Power Reconfigurable Encoder for Flash ADCs

Cited by 9 publications

References 5 publications

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Comparison of Low Power High Speed Comparator for Flash ADC

Darlington CMOS İnverter Tabanlı Paralel Analog-Sayısal Dönüştürücü Tasarımı

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