A Low-Power Multithreaded Processor for Software Defined Radio

Abstract

Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor's architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor's programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.

Instruction set extensions for the advanced encryption standard on a multithreaded software defined radio platform

“…Our AES ISA extensions are implemented in the vector processing unit. The Sandblaster toolchain uses an optimizing ANSI C compiler [25] to generate code for the DSP core. It provides a fast cycle count accurate simulator [25,10], which uses the Sandbridge architecture Description Language (SaDL) to specify the underlying architecture.…”

“…Hence, prevelance in multiple standards and government requirements makes AES a useful protocol to accelerate. While much work has been done to show that sufficient baseband processing capabilities are available in SDRs [25], instruction set architecture (ISA) support for secure SDR has not been a focus of previous research.…”

Amdahl’s Law Revisited for Single Chip Systems

“…The design style of Systems-on-a-Chip (SoCs) has its origins in application specific integrated circuits (ASICs) and embedded system design, which tends to focus on the synthesis of a system for a given application (or set of applications). By contrast, SCHMs such as the Hyperprocessor, (14) the Cell, (15,16) and the Sandblaster (17) are more general hardware solutions, which focus on more general forms of programmability at the system (chip) level. Each has initially focused on a class of applications.…”

An integrated ARM and multi-core DSP simulator

“…The low-power multi-threaded Sandblaster processor [9] offers an efficient and flexible software-defined radio (SDR) platform for wireless communication applications, such as WCDMA with GSM/GPRS capability [6]. To streamline application development, a comprehensive bundle of software tools including simulator, compiler, assembler, debugger, and profiler is provided [5].…”