A Low-Power Multichannel Time-to-Digital Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR Sensors
“…1) We developed comprehensively the mixed-binning (MB) method first proposed in a work-in-progress report [44] (implementing a preliminary 8-channel 50 ps TDC with a measurement range of only 2 ns) to implement a 128-channel resolution-adjustable FPGA-TDC. The proposed TDC delivers excellent linearity and precision performances, even better than recently reported ASIC-TDCs in LiDAR systems [7]- [9]. Moreover, it is costeffective, suitable for commercial applications [43].…”
Section: Introductionmentioning
confidence: 95%
“…ime-to-digital converters (TDCs), or simply high-precision time-sensors, have been widely used in industrial applications, including time-of-flight (ToF) light detection and ranging (LiDAR) in robotics, driverless vehicles, property surveying and landscape mapping [1]- [9], digital synthesizers for enhanced Gigabit Ethernet and wireless communications [10]- [12], thermal management systems for the Internet of Things and semiconductor manufacturing [13]- [15]. TDCs are also critical in time-resolved biomedical imaging techniques such as fluorescence lifetime imaging (FLIM) [16]- [18] and positron emission tomography (PET) [19]- [21].…”
Section: Introductionmentioning
confidence: 99%
“…TDCs in ToF LiDAR systems for robotics and driverless vehicles have different prioritized parameters, especially in the wujun.xie@strath.ac.uk; y.wang.100@strath.ac.uk; haochang.chen@strath.ac.uk; david.li@strath.ac.uk). linearity and the measurement range [7]- [9]. In many applications, LiDAR systems can detect objects' locations and even estimate their speeds and directions of movements [9].…”
Section: Introductionmentioning
confidence: 99%
“…linearity and the measurement range [7]- [9]. In many applications, LiDAR systems can detect objects' locations and even estimate their speeds and directions of movements [9]. Distances between vehicles, for example, measured by a LiDAR system, can range from a few centimeters to hundreds of meters.…”
This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue highlinearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in fieldprogrammable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged − and − are close to or even less than 0.05 LSB in multichannel designs. Index Terms-Light detection and ranging (LiDAR), Timeto-digital converters (TDCs), Time-of-flight (ToF), Fieldprogrammable gate arrays (FPGAs)
“…1) We developed comprehensively the mixed-binning (MB) method first proposed in a work-in-progress report [44] (implementing a preliminary 8-channel 50 ps TDC with a measurement range of only 2 ns) to implement a 128-channel resolution-adjustable FPGA-TDC. The proposed TDC delivers excellent linearity and precision performances, even better than recently reported ASIC-TDCs in LiDAR systems [7]- [9]. Moreover, it is costeffective, suitable for commercial applications [43].…”
Section: Introductionmentioning
confidence: 95%
“…ime-to-digital converters (TDCs), or simply high-precision time-sensors, have been widely used in industrial applications, including time-of-flight (ToF) light detection and ranging (LiDAR) in robotics, driverless vehicles, property surveying and landscape mapping [1]- [9], digital synthesizers for enhanced Gigabit Ethernet and wireless communications [10]- [12], thermal management systems for the Internet of Things and semiconductor manufacturing [13]- [15]. TDCs are also critical in time-resolved biomedical imaging techniques such as fluorescence lifetime imaging (FLIM) [16]- [18] and positron emission tomography (PET) [19]- [21].…”
Section: Introductionmentioning
confidence: 99%
“…TDCs in ToF LiDAR systems for robotics and driverless vehicles have different prioritized parameters, especially in the wujun.xie@strath.ac.uk; y.wang.100@strath.ac.uk; haochang.chen@strath.ac.uk; david.li@strath.ac.uk). linearity and the measurement range [7]- [9]. In many applications, LiDAR systems can detect objects' locations and even estimate their speeds and directions of movements [9].…”
Section: Introductionmentioning
confidence: 99%
“…linearity and the measurement range [7]- [9]. In many applications, LiDAR systems can detect objects' locations and even estimate their speeds and directions of movements [9]. Distances between vehicles, for example, measured by a LiDAR system, can range from a few centimeters to hundreds of meters.…”
This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue highlinearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in fieldprogrammable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged − and − are close to or even less than 0.05 LSB in multichannel designs. Index Terms-Light detection and ranging (LiDAR), Timeto-digital converters (TDCs), Time-of-flight (ToF), Fieldprogrammable gate arrays (FPGAs)
“…However, in the mm-Wave frequency band, due to the capacitor and varactor, the quality factor of the Inductor and Capacitor (LC) tank decreases. blocks [1]. Alternatively, in a Radio Frequency (RF) and mm-Wave transceiver [2], PLL provides the local oscillator signals (LO) for the up-and down-conversion of the RF signals.…”
This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.
This paper proposes wide-range and fast locking all-digital delay-locked loop (WRADDLL) circuit with one cycle dynamic synchronizing. The WRADDLL not only synchronizes the input and output clocks in five clock cycles but maintains one cycle dynamic locking. The WRADDLL reduces the clock skew between the input and output clocks with three innovative techniques. First, by improving the mirror control circuit, the WRADDLL operates correctly with a flexible duty cycle clock signal.Second, the WRADDLL works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Besides, it can achieve one-cycle dynamic locking.Finally, the WRADDLL utilizes the band selector to achieve wide-range operation. After fine tuning, the maximum static phase error is less than 3% of clock cycle. The chip is fabricated by 90 nm standard CMOS process. Its operating frequency range is from 200 MHz to 2 GHz. The power consumption and RMS jitter are 3.24 mW and 1.49 ps at 2 GHz, respectively. The active area of this chip is 0.011 mm 2 .
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