128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

Abstract

This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue highlinearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in fieldprogrammable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged − and − are close to or even less than 0.05 LSB in multichannel designs. Index Terms-Light detection and ranging (LiDAR), Timeto-digital converters (TDCs), Time-of-flight (ToF), Fieldprogrammable gate arrays (FPGAs)

Low-Hardware Consumption, Resolution-Configurable Gray Code Oscillator Time-to-Digital Converters Implemented in 16 nm, 20 nm, and 28 nm FPGAs

“…Industrial applications utilizing time-of-flight (TOF) information (such as LiDAR) concern not only the resolution but also linearity. In time-resolved LiDAR systems, a resolution of 66.6 ps corresponds to a distance of 1 cm [23]. Therefore, LiDAR systems for automatic vehicles and robotics require TDCs with a 35-500 ps resolution and high linearity [24].…”

“…Due to the small propagation delay of carry modules, a TDL often requires more than 200 carry modules to Low hardware consumption, resolutionconfigurable gray code oscillator time-todigital converters implemented in 16nm, 20nm and 28nm FPGAs Yu Wang, Wujun Xie, Haochang Chen, and David Day-Uei Li cover a sampling period. For example, it requires 50 CARRY4s (200 carry modules) in the 7-series FPGA (with a 710MHz sampling clock) [33] and 74 CARRY8s (592 carry modules) in the UltraScale FPGA (with a 500MHz sampling clock) [23].…”

“…When implementing multichannel designs, the consumption of carry modules would be significant (31.26% of CARRY8s are used for 128 channels in Ref. [23]). Besides, in highlyintegrated systems, for example, in LiDAR applications [34], [35], multichannel TDCs are integrated with processing modules in FPGAs.…”

“…For broader applications, TDCs in Ref. [23], [36] and [37] offer flexible resolutions. However, they all need manual configuration channel-by-channel and chip-bychip when resolution requirements change.…”

A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter

“…This method is able to achieve small and uniform bins, however, it increases the complexity and leads to higher utilization of hardware resources. The post-processing method, which has appeared in recent studies, calibrate and compensate for the raw data to improve DNL and Integral Non-Linearity (INL) [2], [29], [33], [34]. However, due to the random variations in the clock skew and process mismatch, the misplacement of time intervals in the raw TDL output remains unpredictable, leading to a permanent loss of temporal information.…”