A low-power dual-mode sigma-delta modulator using charge-steering opamps

A 1.2 V high‐speed low‐power preamplifier latch‐based comparator

“…The supply voltage (VDD) is set to 1.2 V and the sampling rate is set to 100 MHz. The sizes of capacitor C T and capacitor C D are the same as 62.8 fF so that the theoretical value of gain(20 lg(2 C T / C D )) is 6 dB for the charge steering mode preamplifier [9]. The simulation results show that the gain is 6.23 dB and the unit gain bandwidth is 5.23 GHz in Figure 2, meaning that the preamplifiers of both comparators have the similar gain and comparators can operate at higher frequencies.…”

“…The t latch is the time taken by a cross‐coupled latch to regenerate output to settled values. Thus, the t latch is given by [9] $$\begin{equation}{t_{latch\,(a)}} = \frac{{{C_p}_L}}{{{g_{\textit{m,eff}}}}}ln\left( {\frac{{\Delta {V_{out,\textit{final}}}}}{{\Delta {V_{out,{t_0}}}}}} \right) = \frac{{{C_p}_L}}{{{g_{m,\textit{eff}}}}}ln\left( {\frac{{VDD}}{{\Delta {V_{out,{t_{_0}}}}}}} \right)\end{equation}$$ $$\begin{equation}{t_{latch}}_{(b)}{\rm{ }} = \frac{{{C_p}_L}}{{{g_{m,\textit{eff}}}}}ln\left( {\frac{{VDD - Vx}}{{\Delta {V_{out,{t_0}}}}}} \right)\end{equation}$$where C pL is the load capacitance of the latch; g m,eff is the effective transconductance of the back to back inverters; Δ V out,t0 is the initial difference between the output nodes just after amplification at time t 0 ; Δ V out,final is the initial difference between the output nodes after the final of comparison, V x is dropout value of output voltage in the proposed latch, which is very much larger than zero. Therefore, in the proposed latch, we reduce the delay time, that has the greatest impact on the total delay.…”

“…The t latch is the time taken by a cross-coupled latch to regenerate output to settled values. Thus, the t latch is given by [9]…”