A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator

Abstract

This paper presents a low power, high sensitivity Gaussian frequency shift keying (GFSK) demodulator with a flexible frequency offset canceling method for wireless networks for industrial automation process automation (WIA-PA) transceiver fabricated in 0.18 μm CMOS technology. The receiver uses a low-IF (1.5 MHz) architecture, and the transmitter uses a sigma delta PLL based modulation with Gaussian low-pass filter for low power consumption. The active area of the demodulator is 0.14 mm2. Measurement results show that the proposed demodulator operates without harmonic distortion, deals with ± 180 kHz frequency offset, needs SNR only 18.5 dB at 0.1% bit-error rate (BER), and consumes no more than 0.26 mA from a 1.8 V power supply.

A 88μWdigital phase-domain GFSK demodulator compatible with low-IF and zero-IF receiver with preamble detection for BLE

“…Firstly, the implementation of this study mainly consists of digital circuits unlike study in [9,10,12] that mainly constructed by analog circuits. Secondly, the algorithm of this study can demodulate at a low sampling rate of 2 MHz or 4 MHz which keep the dynamic power consumption low unlike the high sampling rate case from study in [6,7].…”

“…The generated pulse is followed by low pass filtering that results in demodulated data. Other limiter technique such as delay-locked loop (DLL) delays clipped IF signal to use as sampling clock in a closed-loop system [9][10][11]. Other technique such as time-to-digital converter (TDC) uses series of coarse and fine delay line to generate sampling clock to track signal's period difference [12][13][14].…”

“…is not included in the design and it is assumed to be provided. In terms of worst SNR performance, DLL demodulator from[9,10] requires SN R of 18.5 dB and 18.7 dB, respectively. As for this work, the 5-bit 2 MHz sampling rate requires SN R of 15 dB while the 5-bit 4 MHz sampling rate demodulator requires SN R of 12.49 dB.…”