A low-power area-efficient SRAM with enhanced read stability in 0.18-μm CMOS

Abstract

Read stability has been considered one of the dominant factors governing the overall performance and operation limitation of static random access memory (SRAM). Furthermore, periodic precharge in read/write (R/W) cycle is the major source of power consumption in an SRAM circuit. To address these two concerns, a newly developed SRAM architecture, with specific concentration on read operation, is described in this paper. By utilizing a "preequalize" scheme, direct connections of the bit lines to power-supply nodes at the beginning of read cycle no longer exist, thereby having the SRAM be provided with an improved power efficiency. The preequalize scheme also yields an increased read static noise margin (SNM) and a cell area comparable to that of the conventional counterpart, due to the similarity between the proposed SRAM cell and familiar inverter circuit in geometry (aspect) ratios of the transistors involved. Several concerns stemming from the proposed scheme are discussed. A 4-kb-capacity prototype designed in a 0.18-µm CMOS process achieves a more power-efficient operation as compared to that adopting conventional architecture.

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“…An ARM Cortex‐A5 with two 16 Kio caches occupies a surface area of 0.53 mm 2 using an etch fineness of 40 nm [40]. A memory such as the RAM used in the tiles occupies a surface area of 1.25 mm 2 [41]. The results are accumulated in Table 3.…”

“…A memory such as the RAM used in the tiles occupies a surface area of 1.25 mm 2 [41]. The results are accumulated in Table 3.…”

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