A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals

Woo, Ramchan; Choi, Sung‐Yool; Sohn, Ju-Ho; Song, Seong-Jun; Bae, Young-Don; Yoo, Hoi‐Jun

doi:10.1109/jssc.2004.829406

Cited by 12 publications

(9 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is important that the slope computation shouldn't be a heavy overhead for interpolation. In many systems [3,6], the slope computation takes a series of subtraction and shift to relieve the need of division hardware or takes ROM and multipliers as the SIMD division unit [7]. [6] restricts the divisor between 2 and 8 to reduce slope computation overhead, including the hardware cost and the number of iteration cycle.…”

Section: Algorithm Level Designmentioning

confidence: 99%

“…Fig.4(b) shows the three main processing stages: span generation, span interpolation, visibility test and texturing. [7] and [8] show different architecture designs for the rendering system. In [7], the architecture takes constant pipelining to control the clock gating at each pipeline stage precisely.…”

Section: Architecture Level Designmentioning

confidence: 99%

“…[7] and [8] show different architecture designs for the rendering system. In [7], the architecture takes constant pipelining to control the clock gating at each pipeline stage precisely. In [8], the processor-based reconfigurable architecture balances the computation loading in rendering system and reduces the total computation time for given tasks.…”

Section: Architecture Level Designmentioning

confidence: 99%

See 2 more Smart Citations

A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance

Chao

Kuo

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

This paper presents a power-aware dynamically reconfigurable rendering engine design, which changes power as rendering throughput and image quality change. At algorithm level, a precisionaware shading scheme is proposed to improve the power efficiency of the conventional shading algorithm through the combination of precision detection and fraction masking techniques. At architecture level, a processing element (PE) based scalable architecture is combined with dynamic task scheduling and dispatching techniques to raise hardware utilization rate and reduce computation latency. Finally a prototyping design which delivers 453MPixels/s, 16.4MTriangles/s, 2.24MPixel/mJ is presented. I.

show abstract

Section: Algorithm Level Designmentioning

confidence: 99%

Section: Architecture Level Designmentioning

confidence: 99%

Section: Architecture Level Designmentioning

confidence: 99%

See 1 more Smart Citation

A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance

Chao

Kuo

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…Another IP provider, Falanx MicrosystemsTm [6], provides the MaliTm Graphics Solution of 3D graphics accelerator IP Cores that support OpenGL ES [7] vi.1 and H.264 functionality and targets different performance, power and die size levels. The GSHARK-TAKUMI's [8] product family lineups graphics engine IP cores for embedded systems and personal information devices such as mobile phones that performing real time display of 3D graphics And also the academic field, there are several outstanding implementations of 3D graphics for consumer electronics [9][10][11][12][13][14][15]. [9,13,14] presented very high performance 3D graphics SoCs with programmability that can fully support OpenGL ES standard API.…”

Section: Introductionmentioning

confidence: 99%

“…[9,13,14] presented very high performance 3D graphics SoCs with programmability that can fully support OpenGL ES standard API. And another research team [12] also implemented a low power 3D graphics engine using DRAM fabrication process that provides very low power consumption.…”

Section: Introductionmentioning

confidence: 99%

A Low Cost Tile-based 3D Graphics Full Pipeline with Real-time Performance Monitoring Support for OpenGL ES in Consumer Electronics

Gu¹,

Yeh²,

Hunag³

et al. 2007

2007 IEEE International Symposium on Consumer Electronics

View full text Add to dashboard Cite

This paper presents a 3D graphics engine which is specifically designed to minimize the hardware cost while providing sufficient computing capability for consumer electronics with small to medium screen sizes (up to 800x600) such as digital television. The presented 3D engine consists ofa fixedfull 3D graphics pipeline for both geometry and rendering operation. This engine provides a standard AHB interface that makes it easily to be integrated into an AMBA-based SoC. The development of the 3D engine has gone through a rigorous design process. startingfrom system modeling (using System-C), RTL implementation, hardwarelsoftware co-simulation and FPGA verification to test chip fabrication. This 3D engine provides 3.3M verticesls and 2 78Mpixels/s in maximum performance at 139 MHz using 0. 18 silicon technology with 987K gates that is sufficient for most applications for digital television. At the same time, a complete OpenGL-ES 1.] API, windowing system, Linux operating system, device driver and a 3D performance monitoring tool have been developedfor our 3D engine. This performance monitoring tool provides run-time performance information include frame rate, triangle rate, pixel rate, involved OpenGL function list, function counts, memory utilization and etc. Moreover, a built-in real-time AHB bus tracer is also provided to monitor the bus activities of the 3D engine and other components on the system bus. The bus tracer captures on-chip bus signals at ether cycle accurate or transaction levels and applies real-time compression to both levels of signals. With the performance monitoring tool and the bus tracer, the 3D application developer can easily analyze the communication of the components and fine tune the 3D application to optimize the entire SoC system performance and to satisfy performancelcost constrains on consumer electronics. Both of the hardware and software have been carefully verified and demonstrated on FPGA using ARM versatile SoC develop board.

show abstract

Shader-based tessellation to save memory bandwidth in a mobile multimedia processor

Chung

Kim

et al. 2009

Computers & Graphics

View full text Add to dashboard Cite

A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals

Cited by 12 publications

References 8 publications

A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance

A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance

A Low Cost Tile-based 3D Graphics Full Pipeline with Real-time Performance Monitoring Support for OpenGL ES in Consumer Electronics

Shader-based tessellation to save memory bandwidth in a mobile multimedia processor

Contact Info

Product

Resources

About