A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS

Biereigel, Stefan; Kulis, Szymon; Leitao, Pedro; Francisco, R.; Moreira, P.; Leroux, Paul; Prinzie, Jeffrey

doi:10.1109/tcsi.2019.2944791

Cited by 13 publications

(17 citation statements)

References 15 publications

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“…This phase error subsequently needs to be corrected by the feedback loop. Again, a mitigation can be found in TMR implementations of the divider [7,9] or by applying Radiation-Hardened-by-Design (RHBD) techniques, such as Double Interlocked Cell (DICE) implementations for memory elements [10].…”

Section: Radiation Effects In Conventional Pll Designsmentioning

confidence: 99%

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Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

et al. 2021

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This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40 MHz to 320 MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11 mW and an FOM of −235 dB.

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Section: Radiation Effects In Conventional Pll Designsmentioning

confidence: 99%

“…Typical MOS varactor tuning architectures have been found to be sensitive to charge collection, as reported in [16]. This sensitivity can be mitigated by adopting a modified tuning topology [9], which, however, has the drawback of introducing an additional pole at the tuning node of the VCO.…”

Section: Radiation Effects In Conventional Pll Designsmentioning

confidence: 99%

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

et al. 2021

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“…As part of the lpGBT, the design specification of the clock generator circuit calls for radiation tolerance up to a TID of 200 Mrad as well as robustness against SEE during operation in the High-Luminosity LHC (HL-LHC) environment. The PLL/CDR circuit is based on the radiation hardened CDR circuit presented in [2]. It was extended by additional circuitry to allow PLL operation and includes a frame aligner compatible with the lpGBT high-speed link specifications [1].…”

Section: Circuit Architecture Radiation Hardening and Operationmentioning

confidence: 99%

“…To compensate for this pole, a feedforward path is added to the loop. To account for process variation and radiation-induced frequency shift, the LC-tank capacitance can be tuned using a Capacitor DAC (CDAC) circuit as presented in [2].…”

Section: Circuit Architecture Radiation Hardening and Operationmentioning

confidence: 99%

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The lpGBT PLL and CDR Architecture, Performance and SEE Robustness

Biereigel¹,

Kulis²,

Francisco³

et al. 2020

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2019)

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We present the design, architecture and experimental results of the low jitter Clock and Data Recovery (CDR) and Phase Locked Loop (PLL) circuit in the Low-Power Gigabit Transceiver (lpGBT) ASIC. This circuit includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. This CDR employs a novel loop architecture with a high-speed feed forward loop stabilization technique. A test circuit was fabricated in a 65 nm CMOS technology and has been tested experimentally for correct operation in the foreseen radiation environment.

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A low jitter sub‐sampling phase‐locked loop with sampling thermal noise cancellation technique

Wang³

et al. 2022

Circuit Theory & Apps

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The traditional sub‐sampling phase‐locked loop faces the tradeoffs between phase noise and spur, in that low in‐band phase noise requires large sampling capacitor size but at the sacrifice of spur performance. This paper presents a sub‐sampling PLL aimed at minimizing in‐band phase noise via sampling thermal noise cancellation technique. It enables the substantial reduction of in‐band phase noise while reducing the sampling capacitor size. In addition, due to the reduction of the sampling capacitance, the reference spur performance of the PLL is improved, and the power consumption of the isolation buffer is reduced. Implemented in a 65 nm CMOS process, the in‐band phase noise at 200 kHz offset is −133.4 dBc/Hz at 2.2 GHz and integrated jitter is 80 fsrms. The reference spur is −67 dBc. It consumes 5.5 mA from 1.2 V supply and occupies 0.72 mm2.

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A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS

Cited by 13 publications

References 15 publications

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

The lpGBT PLL and CDR Architecture, Performance and SEE Robustness

A low jitter sub‐sampling phase‐locked loop with sampling thermal noise cancellation technique

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