A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes

Fan, YouZhe; Xia, ChenYang; Chen, Ji; Tsui, Chi-Ying; Shen, Hui; Li, Bin

doi:10.1109/jsac.2015.2504318

Cited by 46 publications

(56 citation statements)

References 47 publications

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“…A two-staged memory structure similar to the folded partial-sum network in [5] is used. The other parts, including the pointer memory, the CRC unit and the control logic, are similar to their counterparts in the existing architectures [7], [11]. The effective code rate is R = K−r N = 0.494. b Following the method and notation of [11], η determines Au for SE.…”

Section: A the Implementation Of The Proposed Lscd Architecturementioning

confidence: 96%

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An implementation of list successive cancellation decoder with large list size for polar codes

Xia

Fan²,

Chen³

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on the field programmable gate array (FPGA) and significantly impedes the practical deployment of polar codes. To alleviate the high complexity, in this paper, two low-complexity decoding schemes and the corresponding architectures for LSCD targeting FPGA implementation are proposed. The architecture is implemented in an Altera Stratix V FPGA. Measurement results show that, even with a list size of 32, the architecture is able to decode a codeword of 4096-bit polar code within 150 µs, achieving a throughput of 27Mbps.

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Section: A the Implementation Of The Proposed Lscd Architecturementioning

confidence: 96%

“…One common feature of them is that some L× L crossbars are needed to align the data in the L blocks of SCD hardware according to the LM results. Table I shows the synthesis results of the crossbars used in the architecture of [11]. Here, an 8-bit quantization is used for the LLRs.…”

Section: Problems In the Existing Lscd Architecturesmentioning

confidence: 99%

An implementation of list successive cancellation decoder with large list size for polar codes

Xia

Fan²,

Chen³

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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“…Consequently, most of the implementation of the existing ASIC architectures only present results for LSCD with L ≤ 8 [25]- [36], and these architectures are not suitable for LSCD with a large list size. In our previous work [39], [40], a double thresholding scheme (DTS) was proposed, in which an approximate sorting method is used with the help of two run-time generated threshold values. By doing this, the sorting and hence the selection of the best L paths do not scale with L and the scheme is suitable for LSCD with a large list size.…”

Section: Introductionmentioning

confidence: 99%

“…For LSCD with L = 32, only CPU-based [37] and FPGA-based [41] architectures have been proposed and no ASIC architecture has been reported. Further optimization methods that selectively expand the paths at each bit and eliminate unnecessary execution times of LM operations [36], [40]- [42] were proposed to reduce the overall latency.…”

Section: Introductionmentioning

confidence: 99%

A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size

Xia

Chen

Fan

et al. 2018

IEEE Trans. Signal Process.

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As the first kind of forward error correction (FEC) codes that achieve channel capacity, polar codes have attracted much research interest recently. Compared with other popular FEC codes, polar codes decoded by list successive cancellation decoding (LSCD) with a large list size have better error correction performance. However, due to the serial decoding nature of LSCD and the high complexity of list management (LM), the decoding latency is high, which limits the usage of polar codes in practical applications that require low latency and high throughput. In this work, we study the high-throughput implementation of LSCD with a large list size. Specifically, at the algorithmic level, to achieve a low decoding latency with moderate hardware complexity, two decoding schemes, a multi-bit double thresholding scheme and a partial G-node look-ahead scheme, are proposed. Then, a high-throughput VLSI architecture implementing the proposed algorithms is developed with optimizations on different computation modules. From the implementation results on UMC 90 nm CMOS technology, the proposed architecture achieves decoding throughputs of 1.103 Gbps, 977 Mbps and 827 Mbps when the list sizes are 8, 16 and 32, respectively.

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“…Polar codes, invented by Arıkan [1], are proved to be capacity-achieving under successive cancellation (SC) decoder over binary-input discrete memoryless channels (B-DMCs). For finitelength cases, it is found that concatenated with cyclic redundancy check (CRC) codes, polar code under SC list (SCL) decoding achieves competitive performance to turbo codes or low-density parity-check codes (despite that the decoding complexity of polar associated with list decoding is subject to further studies to make it practically appealing) [2] [3][4] [5]. Therefore, polar code is a competitive candidate in future communication systems and has been adopted as the coding scheme for control channels for the 5G cellular system.…”

Section: Introductionmentioning

confidence: 99%

ARUM: Polar-Coded HARQ Scheme Based on Incremental Channel Polarization

Chen¹,

Wu²,

Xu³

et al. 2018

IEEE Commun. Lett.

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A hybrid ARQ (HARQ) scheme for polar code, which is called active-bit relocation under masks (ARUM), is proposed. In each transmission, the data bits are encoded and bit-wisely XOR-masked using a binary vector before being transmitted through the channel. The masking process combines multiple transmissions together which forms another step of inter-transmission channel transform. The reliabilities are updated after every transmission, and the less reliable bits in earlier ones are relocated to the more reliable positions at the latest transmitted block. ARUM is a very flexible HARQ scheme which allows each transmission to have a different mother code length and to adopt independent rate-matching scheme with sufficient channel state feedback in HARQ process. Simulation shows that ARUM can obtain near-optimal coding gain.

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A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes

Cited by 46 publications

References 47 publications

An implementation of list successive cancellation decoder with large list size for polar codes

An implementation of list successive cancellation decoder with large list size for polar codes

A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size

ARUM: Polar-Coded HARQ Scheme Based on Incremental Channel Polarization

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