A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size

Abstract

As the first kind of forward error correction (FEC) codes that achieve channel capacity, polar codes have attracted much research interest recently. Compared with other popular FEC codes, polar codes decoded by list successive cancellation decoding (LSCD) with a large list size have better error correction performance. However, due to the serial decoding nature of LSCD and the high complexity of list management (LM), the decoding latency is high, which limits the usage of polar codes in practical applications that require low latency and high throughput. In this work, we study the high-throughput implementation of LSCD with a large list size. Specifically, at the algorithmic level, to achieve a low decoding latency with moderate hardware complexity, two decoding schemes, a multi-bit double thresholding scheme and a partial G-node look-ahead scheme, are proposed. Then, a high-throughput VLSI architecture implementing the proposed algorithms is developed with optimizations on different computation modules. From the implementation results on UMC 90 nm CMOS technology, the proposed architecture achieves decoding throughputs of 1.103 Gbps, 977 Mbps and 827 Mbps when the list sizes are 8, 16 and 32, respectively.

A 506Gbit/s Polar Successive Cancellation List Decoder with CRC

“…This approach is not suitable for our framework, since the limit for the processing of one stage is one clock-cycle. The same accounts for the procedure presented in [22], where also multiple clock-cycles are needed.…”

A Two-Staged Adaptive Successive Cancellation List Decoding for Polar Codes

“…The list sizes of the two component SCL decoders are L s = 1 and L l = 32, respectively. The simulated BLER results of D TA under different speed gain and buffer sizes are obtained at an SNR of 2dB and are compared with the upper bounds calculated using (1) and (8). Fig.…”

“…Due to the extraordinary error correction performance of CRC-aided SCL decoding, its hardware implementation has attracted much research interest recently. Several different VLSI architectures [8]- [16] have been proposed for SCL. The decoding throughputs achieved by the state-of-the-art architectures are shown in Fig.…”

“…This algorithm first uses a single SC to decode a codeword. If the decoded vector List size Throughput (Gbps) TSP18' [8] TSP17' [13] TVLSI16' [12] cannot pass CRC, the list size is doubled and the decoding repeats. This process is iterated until a valid vector is obtained or a pre-defined L max is reached.…”

An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture

“…One approach is to prune the SC decoding tree by decoding multi-bit subcodes at the same time so that fewer list management (LM) operations are needed. Parallel decoded sub-codes can be either general codes comprised of consecutive M = 2 m bits [8]- [10] or matching a special code pattern with variable length [11]- [14]. The first kind decodes M bits simultaneously, where M is a fixed and predefined value.…”