An implementation of list successive cancellation decoder with large list size for polar codes

Abstract

Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on the field programmable gate array (FPGA) and significantly impedes the practical deployment of polar codes. To alleviate the high complexity, in this paper, two low-complexity decoding schemes and the corresponding architectures for LSCD targeting FPGA implementation are proposed. The architecture is implemented in an Altera Stratix V FPGA. Measurement results show that, even with a list size of 32, the architecture is able to decode a codeword of 4096-bit polar code within 150 µs, achieving a throughput of 27Mbps.

A Complexity Reduction Method for Successive Cancellation List Decoding

“…As seen from the implementation results, the simplified decoder with the proposed sorting method can achieve larger throughput than that of [35] with significantly lower memory consumption. On the other hand, the decoder in [35] can operate with larger list sizes owing to the lack of crossbars with large input widths. The results show that the proposed method offers a balanced decoder design with reasonable hardware complexity and throughput, especially for large block lengths.…”

“…More specifically, the proposed method can support twice the list size, which requires approximately four times as large hardware resources as observed from the results in Table II, for a four times as large block length with similar hardware resources and throughput. The decoder in [35] achieves hardware complexity reduction by completely eliminating decoded bit and partialsum crossbars at the expense of increased latency. Therefore, the decoder in [35] has a higher latency even though it benefits from multibit decoding (MBD) [14] and switches to parallel decoding at low decoding stages to achieve latency reduction.…”

“…The decoder in [35] achieves hardware complexity reduction by completely eliminating decoded bit and partialsum crossbars at the expense of increased latency. Therefore, the decoder in [35] has a higher latency even though it benefits from multibit decoding (MBD) [14] and switches to parallel decoding at low decoding stages to achieve latency reduction. As seen from the implementation results, the simplified decoder with the proposed sorting method can achieve larger throughput than that of [35] with significantly lower memory consumption.…”

A Two-Staged Adaptive Successive Cancellation List Decoding for Polar Codes

“…Due to the extraordinary error correction performance of CRC-aided SCL decoding, its hardware implementation has attracted much research interest recently. Several different VLSI architectures [8]- [16] have been proposed for SCL. The decoding throughputs achieved by the state-of-the-art architectures are shown in Fig.…”

A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size

“…Implementation results show that the architecture of LSCD with L = 16 using the DTS doubled the decoding throughput and the list size when compared with the stateof-the-art architectures at that time. For LSCD with L = 32, only CPU-based [37] and FPGA-based [41] architectures have been proposed and no ASIC architecture has been reported. Further optimization methods that selectively expand the paths at each bit and eliminate unnecessary execution times of LM operations [36], [40]- [42] were proposed to reduce the overall latency.…”