A low-cost modular SiGe BiCMOS technology and analog passives for high-performance RF and wide-band applications

Tang, Ruihua; Leung, Chi-Wai; Nguyen, Diep N.; Hsu, Terng-Ren; Fritzinger, L.B.; Molloy, Stephen; Esry, T.; Ivanov, Ts.; Chu, J.; Carroll, Michael S.; Huang, Ji-Cheng; Möller, W.; Campbell, T.; King, C. A.; Frei, M.; Mastrapasqua, M.; Ng, K. K.; Chen, C.; Johnson, Richard W.; Pullela, R.; Archer, V.D.; Krska, J.Y.; Moinian, S.; Cong, H.-I.

doi:10.1109/bipol.2000.886183

Cited by 13 publications

(4 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Currently, chip manufacturers focus mainly on the integration of Si 1Ϫx Ge x in heterojunction bipolar transistors ͑HBT͒ in Bi complementary metal oxide semiconductor ͑BiCMOS͒ technology. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] In a next phase, attention goes to the fabrication of Si/Si 1Ϫx Ge x heterojunction CMOS devices to improve the performance of the p-type metal oxide semiconductor ͑MOS͒ device, [16][17][18][19][20][21][22][23][24] and to elevated Si 1Ϫx Ge x source/drain contacts to reduce short channel effects in CMOS technology. [25][26][27][28][29] For the first two applications, both selective and nonselective epitaxial growth by means of chemical vapor deposition ͑CVD͒ can be used.…”

mentioning

confidence: 99%

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Loo

Caymax

Peytier

et al. 2003

J. Electrochem. Soc.

View full text Add to dashboard Cite

Si 1Ϫx Ge x /Si heterostructures are useful for numerous device applications where device performance is improved by band offsets and/or increased carrier mobility. The use of selective epitaxial growth for the implementation of Si 1Ϫx Ge x has some advantages compared to a nonselective growth process. However, some issues such as thickness nonuniformity ͑microloading on a micrometer scale and gas depletion on a wafer scale͒ and facet formation must be solved. In this paper, we give a detailed overview of our selective Si 1Ϫx Ge x growth process in a standard production-oriented chemical vapor deposition system for Ge contents between 0 and 32%. Our process allows layer deposition with no pattern dependence of the growth rate and Ge content ͑no microloading͒ and with a wafer scale layer nonuniformity that is better than the accuracy of the measurement techniques (ϳ2%). Facet formation was avoided by choosing the correct growth conditions and by preventing lateral growth over the mask material. Selective epitaxial layers did not show a degradation of photoluminescence characteristics. The layer quality is further demonstrated by the performance of Si 1Ϫx Ge x heterojunction bipolar transistors ͑0.35 and 0.25 m technology͒, and p-type Si 1Ϫx Ge x heterojunction metal oxide semiconductor devices ͑effective gate length down to 70 nm͒.

show abstract

mentioning

confidence: 99%

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Loo

Caymax

Peytier

et al. 2003

J. Electrochem. Soc.

View full text Add to dashboard Cite

show abstract

“…The photo-resist layer is specially treated by extended thermal baking and UV hardening before HEI to prevent resist cracking and peeling during HEI [5].…”

Section: Process Integration Of the Sige Devicementioning

confidence: 99%

“…Several resistors are available in BiCMOS process technology and are summarized in Table 3 [5]. Gate poly, n + and p + source/drain, and n-tub resistors are characterized from the digital CMOS process.…”

Section: Resistorsmentioning

confidence: 99%

“…The p + layer has a resistivity of roughly 0.01 Ω-cm and plays an important role in latch-up suppression and impurity gettering (attracting heavy metals away from the silicon surface) in CMOS devices. The simple solution of changing to a bulk p − substrate [ Figure 14(b)] enables the fabrication of high-Q inductors [5] but may exact a price in reduced device density (to prevent device latch up) and possible yield loss. Also, many of the reuse advantages in SOC integration would be voided by, perhaps, resulting shifts in device characteristics and changed design rules required to satisfy the latch-up conditions.…”

Section: Integration Of High-q Inductors In a Latch-up Resistant Cmosmentioning

confidence: 99%

See 1 more Smart Citation

BiCMOS technology for mixed-digital, analog, and RF applications

Rich

Carroll²,

Frei³

et al. 2002

IEEE Microwave

Self Cite

View full text Add to dashboard Cite

A 0.2-μm 180-GHz-f/sub max/ 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications

Washio

Ohue

Shimamoto

et al. 2002

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

A low-cost modular SiGe BiCMOS technology and analog passives for high-performance RF and wide-band applications

Cited by 13 publications

References 1 publication

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

BiCMOS technology for mixed-digital, analog, and RF applications

A 0.2-μm 180-GHz-f/sub max/ 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications

Contact Info

Product

Resources

About