A low-cost, leakage-insensitive semi-digital PLL with linear phase detection and FIR-embedded digital frequency acquisition

Abstract

A semi-digital PLL utilizing a hybrid DCO is presented. A mixed-mode loop control with an analog proportional path and a digital integration path provides linear phase tracking, leakage-insensitive loop filtering, and technology scalability. With the absence of the linear TDC, the semi-digital PLL with the hybrid DCO can relax design difficulties such as achieving low power or requiring an advanced CMOS technology. Also, the hybrid finite-impulse response (FIR) filtering method is employed to reduce the DCO quantization noise without causing latency. The prototype PLL implemented in 0.18μm has the active area of 0.6mm 2 where only 0.01mm 2 is occupied by the analog loop filter.I.

A wideband low-jitter PLL with an optimized Ring-VCO

“…In [13,14,15,16,17], injection-locked PLLs are employed to reduce the jitter, however, additional calibration circuits are usually required to guarantee the optimal performance and the correct operation. An attractive method uses hybrid loops to achieve low jitter PLLs [18,19,20], as well as results in rather complicated circuits. More and more digital PLLs [21,22,23,24,25,26] are designed due to the advantages in terms of power, area, and programmability, whereas the improvement is needed in the jitter performance of digital PLLs.…”