A low cost architecture for high performance face detection

Zhou, Weina; Wu, Huafeng; Zeng, Xiaoyang

doi:10.1016/j.micpro.2015.05.016

Cited by 1 publication

(1 citation statement)

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“…In the architecture, the systolic array implementation is used to boost the parallel computation of the classifiers and parallelize the calculation of the window integral image. In some architectures, the current window integral image can be generated in one clock cycle, due to the correlation between the integral images of the adjacent windows [31], [35]. In the work [36], a heterogeneous system integrated by the ARM and FPGA platform is proposed to accelerate the AdaBoost-based detector.…”

Section: Introductionmentioning

confidence: 99%

Parallelism Optimized Architecture on FPGA for Real-Time Traffic Light Detection

Bao

2019

IEEE Access

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In this paper, a portable assistance system is designed to help the visually impaired to detect the traffic light. The designed system is realized on the basis of the AdaBoost algorithm, which is fast and robust in object detections. In order to accelerate the AdaBoost-based approach, a flexible parallel architecture is implemented on the field-programmable gate array (FPGA) platform. The architecture is designed utilizing the parallelism of computations in the AdaBoost-based detection. The computations of the window integral image are implemented in parallel, and the confidences of the weak classifiers are calculated in parallel. The parameters of the weak classifiers are trained by the AdaBoost algorithm with multi-layer features in the MATLAB software, and then are configured on the FPGA platform via the Vivado design suite before the detection process. The parallelism optimized architecture is implemented on an Artix-7 FPGA at 200 MHZ. Experiments show that it can detect the traffic light in videos with a rate of 30 frames per second (fps).INDEX TERMS AdaBoost algorithm, field-programmable gate array, integral image, parallel architecture, traffic light detection.

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Section: Introductionmentioning

confidence: 99%

Parallelism Optimized Architecture on FPGA for Real-Time Traffic Light Detection

Bao

2019

IEEE Access

View full text Add to dashboard Cite

show abstract

A low cost architecture for high performance face detection

Cited by 1 publication

References 18 publications

Parallelism Optimized Architecture on FPGA for Real-Time Traffic Light Detection

Parallelism Optimized Architecture on FPGA for Real-Time Traffic Light Detection

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