A low-cost, 300-MHz, RISC CPU with attached media processor

Santhanam, S.; Baum, A.J.; Bertucci, D.; Braganza, M.; Broch, K.; Broch, T.; Burnette, James E.; Chang, Eric Y.; Chui, Kwong-Tak; Dobberpuhl, D.; Donahue, P.; Grodstein, J.; Kim, In-Sung; Murray, D.; Pearce, M.; Silveria, A.; Souydalay, D.; Spink, A.; Stepanian, R.; Varadharajan, A.; Kaenel, V.R. van; Wen, R.

doi:10.1109/4.726584

Cited by 38 publications

(7 citation statements)

References 5 publications

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“…For most of these designs, detailed power consumption analysis has not been disclosed; therefore to asses our design methodology, we compare the energy and area efficiency of the SVD chips to published baseband and media processors [32]- [39]. To make the comparison fair, the data rate and power are normalized to a 1 V 90 nm technology, and 12-bit wordlengths.…”

Section: Energy and Area Efficiencymentioning

confidence: 99%

Power and Area Minimization for Multidimensional Signal Processing

Marković

Nikolić

Brodersen

2007

IEEE J. Solid-State Circuits

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Abstract-Sensitivity-based methodology is applied to optimization of performance, power and area across several levels of design abstraction for a complex wireless baseband signal processing algorithm. The design framework is based on a unified, block-based graphical description of the algorithm to avoid design re-entry in various phases of chip development. The use of architectural techniques for minimization of power and area for complex signal processing algorithms is demonstrated using this framework. As a proof of concept, an ASIC realization of the MIMO baseband signal processing for a multi-antenna WLAN is described. The chip implements a 4 4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1 GOPS/mW (12-bit add equivalent) in just 3.5 mm 2 in a standard 90 nm CMOS process. The computational throughput of 70 GOPS is implemented with 0.5 M cells at a 100 MHz clock and 385 mV supply, dissipating 34 mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250 Mb/s over 16 sub-carriers.

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Section: Energy and Area Efficiencymentioning

confidence: 99%

Power and Area Minimization for Multidimensional Signal Processing

Marković

Nikolić

Brodersen

2007

IEEE J. Solid-State Circuits

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“…In most microprocessor designs, caches dissipate a significant fraction of total power. For example, the Alpha 21264 dissipates 16% [12] and the StrongArm dissipates more than 43% [19] of overall power in caches. As a result, there has been great interest in reducing cache power consumption.…”

Section: Introductionmentioning

confidence: 99%

Fine-grain CAM-tag cache resizing using miss tags

Zhang¹,

Asanović²

2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design - ISLPED '02

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A new dynamic cache resizing scheme for low-power CAMtag caches is introduced. A control algorithm that is only activated on cache misses uses a duplicate set of tags, the miss tags, to minimize active cache size while sustaining close to the same hit rate as a full size cache. The cache partitioning mechanism saves both switching and leakage energy in unused partitions with little impact on cycle time. Simulation results show that the scheme saves 28-56% of data cache energy and 34-49% of instruction cache energy with minimal performance impact.

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“…We reduce the number of active bitlines with local word lines that enable only the required 32-bit segment of any row on any CPU access; we only enable all 128 bit columns during cache refills. In addition, a self-timed circuit is used to limit the voltage swing of bitlines during read accesses by pulsing the word lines [1,5]; this reduces bitline swing to around 15% of full rail. The CPU to cache interface is a Table 2: Breakdown of energy consumption for 32-bit accesses in base line cache design.…”

Section: Baseline Cache Designmentioning

confidence: 99%

“…In a differential design, one of the two bitlines must be discharged for each access regardless of the stored data value. The energy penalty for reads can be reduced by employing a pulsed-word-line technique to turn off the word lines when a sufficient voltage differential has developed on the bitlines [1,5]. Writes to an SRAM are also usually performed differentially but typically require a full voltage swing on the bitlines and hence consume considerably more energy than low-voltage-swing reads.…”

Section: Introductionmentioning

confidence: 99%

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Dynamic zero compression for cache energy reduction

Villa¹,

Zhang²,

Asanović³

2000

Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture

134

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Dynamic Zero Compression reduces the energy required for cache accesses by only writing and reading a single bit for every zero-valued byte. This energy-conscious compression is invisible to software and is handled with additional circuitry embedded inside the cache RAM arrays and the CPU. The additional circuitry imposes a cache area overhead of 9% and a read latency overhead of around two FO4 gate delays. Simulation results show that we can reduce total data cache energy by around 26% and instruction cache energy by around 10% for SPECint95 and MediaBench benchmarks. We also describe the use of an instruction recoding technique that increases instruction cache energy savings to 18%.

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A low-cost, 300-MHz, RISC CPU with attached media processor

Cited by 38 publications

References 5 publications

Power and Area Minimization for Multidimensional Signal Processing

Power and Area Minimization for Multidimensional Signal Processing

Fine-grain CAM-tag cache resizing using miss tags

Dynamic zero compression for cache energy reduction

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