Dynamic zero compression for cache energy reduction

Villa, Luis; Zhang, Michael; Asanović, Krste

doi:10.1145/360128.360150

Cited by 134 publications

(63 citation statements)

References 11 publications

(12 reference statements)

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“…This cache model, initally presented by Ghose and Kamble [9], is based in a subbanking scheme and has the advantage that each word (within a cache line) can be read independently without the need to read the whole cache line. The same model was used by Villa et al [22] in their dynamic zero compression scheme. The results of the PA-DFVC, in terms of Energy-Delay Product and power reduction, are presented in Section 5.2.…”

Section: Fig 4 Hp-dfvc: Detailed Designmentioning

confidence: 99%

“…Cache/Memory compression has been proposed for better utilization of the available transistor budgets [1,13,22]. The idea behind this approach is to store cache lines in a compressed form so a greater number of cache lines can reside in the cache at any given time, lowering the miss rate.…”

Section: Design Issues Of High-performance Dfvc (Hp-dfvc)mentioning

confidence: 99%

“…The idea behind such schemes is simple: unused storage cells and wires provide a benefit simply by not consuming power. In the Dynamic Zero Compression scheme [22], each zero valued byte is represented by a single bit. Another approach for power/energy reduction was by Kim et al [13].…”

Section: Related Workmentioning

confidence: 99%

“…L2/L3 compression is therefore a useful technique for the foreseeable future and especially for future CMP architectures. Alternatively, compression can be used to free space in the cache which can then be translated to power savings [13,22,23,25].…”

Section: Introductionmentioning

confidence: 99%

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Dynamic Dictionary-Based Data Compression for Level-1 Caches

Κεραμίδας

Aisopos

2006

Architecture of Computing Systems - ARCS 2006

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Abstract. Data cache compression is actively studied as a venue to make better use of onchip transistors, increase apparent capacity of caches, and hide the long memory latencies. While several techniques have been proposed for L2 compression, L1 compression is an elusive goal. This is due to L1's sensitivity to latency and the inability to create compression schemes that are both fast and adaptable to program behavior, i.e. dynamic. In this paper, we propose the first dynamic dictionary-based compression mechanism for L1 data caches. Our design solves the problem of keeping the compressed contents of the cache and the dictionary entries consistent, using a timekeeping decay technique. A dynamic compression dictionary adapts to program behavior without the need of profiling techniques and/or training phases. We compare our approach to previously proposed static dictionary techniques and we show that we surpass them in terms of power, hit ratio and energy delay product.

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Section: Fig 4 Hp-dfvc: Detailed Designmentioning

confidence: 99%

Section: Design Issues Of High-performance Dfvc (Hp-dfvc)mentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Dynamic Dictionary-Based Data Compression for Level-1 Caches

Κεραμίδας

Aisopos

2006

Architecture of Computing Systems - ARCS 2006

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“…In addition, dynamic data compression techniques ( [14], [15]) have been proposed as a way to reduce energy consumption in processor units. They are orthogonal to the design proposed here.…”

Section: Related Workmentioning

confidence: 99%

A Simple Low-Energy Instruction Wakeup Mechanism

García-Ramírez

Cristal²,

Veidenbaum

et al. 2003

Lecture Notes in Computer Science

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Abstract. Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for instruction wakeup, which uses a multi-block instruction queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed instruction for SPEC2000 benchmarks.

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Reducing Cache Hardware by Focusing on Data Redundancy

Kobayashi

Matsukawa

Shimomura

et al. 2014

Elect Comm in Japan

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SUMMARY There is one reason to utilize cache that mitigates processor performance limitation comes from data transfer bandwidth. Recently, cache size expansion is required in this use because data transfer bandwidth requirement is increasing for recent large data size and multi‐core trends. However, cache size expansion is unwelcome because it causes problems arising from circuit area and power consumption viewpoint. This paper focuses a data redundancy with the goal of reducing cache size and proposes a mechanism that does not store redundant data into cache. The proposed mechanism divides data into higher bit and lower bit that stored into higher cache and lower cache, respectively. We reduced higher cache size to half size by keeping 46% redundant data in higher bit area not to store into higher cache. The evaluation results show that the proposed mechanism increases IPC by 3.3% on average compared with same circuit area conventional cache under SPECCPU2000 benchmarks.

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Dynamic zero compression for cache energy reduction

Cited by 134 publications

References 11 publications

Dynamic Dictionary-Based Data Compression for Level-1 Caches

Dynamic Dictionary-Based Data Compression for Level-1 Caches

A Simple Low-Energy Instruction Wakeup Mechanism

Reducing Cache Hardware by Focusing on Data Redundancy

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