A loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology

Noda, K.; Matsui, K.; Takeda, Koichi; Nakamura, N.

doi:10.1109/16.974716

Cited by 48 publications

(26 citation statements)

References 3 publications

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“…Previous work on random threshold voltage variations between neighboring, small geometry SRAM cell transistors due to dopant fluctuations [1][2][3][4], line edge roughness [5] and poly gate grain size variations [6] have been shown to limit the DC Read stability of SRAMs [7][8][9][10]. The impact of VT fluctuations on SRAM cell DC write margins is reported in this work, for the first time, and is shown to be the more limiting case.…”

Section: Introductionmentioning

confidence: 69%

Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells

Bhavnagarwala

Kosonocky

Radens

et al.

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

141

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Section: Introductionmentioning

confidence: 69%

Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells

Bhavnagarwala

Kosonocky

Radens

et al.

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

141

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“…One classical cell is left out of the overview: the no load 4T cell as discussed in [7]. The retention current of this cell is actually the leakage current of its access transistors, which needs to be accurately controlled.…”

Section: B Variability Effectsmentioning

confidence: 99%

Embedded SRAM design in deep deep submicron technologies

Dehaene

Cosemans

Vignon

et al. 2007

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

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Static RAM memory is more than ever a key component in systems on chip. Static memories are dominating factors in the cost, the performance and the energy consumption of such systems. Deep deep submicron scaling beyond 130 nm complicates the design of SRAM circuits that make a good compromise between performance and energy consumption. This is mainly caused by leakage and technological variability. The effect of leakage and variability is amplified by the fact that large area penalties are unacceptable for cost reasons. As a consequence, novel circuit designs are needed to alleviate the additional problems introduced by advanced scaling while keeping classic scaling advantages intact. This paper gives an overview of circuit techniques that have recently been proposed to improve the position of SRAMS in the area-energy-performance design space. This paper starts from the SRAM cell, expands to the local bitline to conclude with the circuit architecture of complete SRAMs.

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“…Basic four-transistor (4T) DRAM cells are well established and described in introductory VLSI textbooks and various articles [30], [32], [41]. 4T cells are similar to ordinary 6T cells but lack two transistors connected to q r r that replenish the charge that is lost via leakage ( Figure 15).…”

Section: A the Quasi-static 4t Cellmentioning

confidence: 99%

Implementing branch-predictor decay using quasi-static memory cells

Juang

Skadron

Martonosi

et al. 2004

ACM Trans. Archit. Code Optim.

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With semiconductor technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large on-chip array structures such as caches and branch predictors. Recent work has suggested that even larger branch predictors can and should be used in order to improve microprocessor performance. A further consideration is that more aggressive branch predictors, especially multiported predictors for multiple branch prediction, may be thermal hot spots, thus further increasing its leakage. Moreover, as the branch predictor holds state that is transient and predictive, elements can be discarded without adverse effect. For these reasons, it is natural to consider applying decay techniques-already shown to reduce leakage energy for caches-to branch-prediction structures.Due to the structural difference between caches and branch predictors, applying decay techniques to branch predictors is not straightforward. This paper explores the strategies for exploiting spatial and temporal locality to make decay effective for bimodal, gshare, and hybrid predictors, as well as the branch target buffer. Furthermore, the predictive behavior of branch predictors steers them towards decay based not on state-preserving, static storage cells, but rather quasi-static, dynamic storage cells. This paper will examine the results of implementing decaying branch predictor structures with dynamic-appropriately, decaying-cells rather than the standard static SRAM cell.Overall, this paper demonstrates that decay techniques can apply to more than just caches, with the branch predictor and BTB as an example. We show decay can either be implemented at the architectural level, or with a wholesale replacement of static storage cells with quasi-static storage cells which naturally implement decay. More importantly, decay techniques can be applied and should be applied to other such transient and/or predictive structures.

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A loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology

Cited by 48 publications

References 3 publications

Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells

Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells

Embedded SRAM design in deep deep submicron technologies

Implementing branch-predictor decay using quasi-static memory cells

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