A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes

Sachid, Angada B.; Hu, Chenming

doi:10.1109/soi.2012.6404367

Cited by 11 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…and an inversion mode capacitance [C(inv.)] depending on the inverter bias condition [19][20][21]. Thus, the Cin and the Cout can be expressed as below.…”

Section: B Capacitance Analysismentioning

confidence: 99%

Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application

Kim

Lee

et al. 2023

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

In this paper, floating fin structured vertically stacked nanosheet gate-all-around (GAA) metal oxide semiconductor field-effect transistor (FNS) is proposed for low power logic device applications. To verify the electrical performance of the proposed device, three-dimensional (3-D) technology computer-aided design (TCAD) device/circuit simulations are performed with calibrated device model parameters. As a result, it is found that gate propagation delay (τdelay) and dynamic power (Pdyn) are improved by 8% and 19%. respectively as compared to conventional vertically stacked lateral nanosheet (LNS). Through the rigorous analysis on the resistance and capacitance components of FNS and LNS, it is clearly revealed that the τdelay and Pdyn are improved at the same Pdyn (50 μW) and τdelay (187 GHz) by the reduced effective capacitance which results from the diminished gate-to-sorece/drain overlap area. Based on the TCAD simulation studies, it is expected that the FNS is suitable for next generation logic digital applications.

show abstract

“…and an inversion mode capacitance [C(inv.)] depending on the inverter bias condition [19][20][21]. Thus, the Cin and the Cout can be expressed as below.…”

Section: B Capacitance Analysismentioning

confidence: 99%

Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application

Kim

Lee

et al. 2023

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…Until now, the has not yet been considered. Analysis from UC Berkeley has found that propagation delay in FinFET circuits is independent of electrical width [19]. This serves to maintain the gain of inverter built with FinFET devices, even as they are scaled.…”

Section: A τ and F O4 Delaymentioning

confidence: 99%

Dynamic synchronizer flip-flop performance in FinFET technologies

Buckler¹,

Vaidya

Liu

et al. 2014

2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

View full text Add to dashboard Cite

The use of fine-grain Dynamic Voltage and Frequency Scaling (DVFS) has increased the number of distinct clock domains on a given Network-on-Chip (NoC). This necessitates robust synchronizers to prevent clock domain communication failures, even as FinFET devices have begun to replace planar devices. This paper presents simulation results and comparisons between dynamic (requiring reset) and non-dynamic synchronizer flip-flops implemented in predictive models for both planar technologies and future FinFET technologies. Results demonstrate that synchronizers built with FinFET devices 1) exhibit a tau value which continues to scale with fan-out of four delay and 2) can be improved with forward biasing, but 3) are more sensitive to temperature. Dynamic flip-flops settled metastability fastest when using standard technology voltages, but previously couldn't be used in non-dynamic systems. For this reason, a new synchronizer design is also presented which exploits the benefits of dynamic flip-flops without the need for a dedicated reset signal.

show abstract