Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application

Abstract

In this paper, floating fin structured vertically stacked nanosheet gate-all-around (GAA) metal oxide semiconductor field-effect transistor (FNS) is proposed for low power logic device applications. To verify the electrical performance of the proposed device, three-dimensional (3-D) technology computer-aided design (TCAD) device/circuit simulations are performed with calibrated device model parameters. As a result, it is found that gate propagation delay (τdelay) and dynamic power (Pdyn) are improved by 8% and 19%. respectively as compared to conventional vertically stacked lateral nanosheet (LNS). Through the rigorous analysis on the resistance and capacitance components of FNS and LNS, it is clearly revealed that the τdelay and Pdyn are improved at the same Pdyn (50 μW) and τdelay (187 GHz) by the reduced effective capacitance which results from the diminished gate-to-sorece/drain overlap area. Based on the TCAD simulation studies, it is expected that the FNS is suitable for next generation logic digital applications.

Parameter extraction using the transfer characteristics of vertically stacked Si nanosheet MOSFETs

“…The unrelenting evolution of increasingly complex 3D transistor structures, as well as the enormous progress of advanced IC fabrication technologies, such as those that have enabled the commercial manufacture of FinFETs, has inspired the emergence of other innovative Gate-All-Around (GAA) device structures, such as nanowire FETs and lately vertically stacked NanoSheet MOSFETs [1], [2] as a promising strategy to further IC component miniaturization [3].…”