A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

Koibuchi, Michihiro; Matsutani, Hiroki; Amano, Hideharu; Pinkston, Timothy M.

doi:10.1109/nocs.2008.4492721

Cited by 107 publications

(43 citation statements)

References 18 publications

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“…Faulty channels can be disabled which forces packets to use alternate and often longer paths [29,40]. To increase a channel's tolerance to silicon defects, spare channel bits can be associated with every channel [10,52,25].…”

Section: Background and Related Workmentioning

confidence: 99%

Variable-width datapath for on-chip network static power reduction

Shalf

2014

2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

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Section: Background and Related Workmentioning

confidence: 99%

Variable-width datapath for on-chip network static power reduction

Shalf

2014

2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

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“…Also research on router design to improve reliability [32], buffer flow control [33] and error correction techniques [34,35] for NoC have been proposed. Koibuchi et al [36] proposed a lightweight fault-tolerant mechanism called default backup path (DBP). The approach proposed a solution for non-faulty routers and healthy PEs.…”

Section: Mpsoc Design Literature Reviewmentioning

confidence: 99%

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Tafesse

Muthukumar

2013

VLSI Design

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Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.

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“…Duato's solution [23] can handle (n − 1) faults in a n-dimensional mesh while Gomez et al [24] tolerate up to five faults using additional virtual channels. The work in [25] can potentially sustain several faults: the authors provides a backup path around each failed router. As faults accumulate, backup paths form a ring topology.…”

Section: Related Workmentioning

confidence: 99%

A Reliable Routing Architecture and Algorithm for NoCs

DeOrio

Fick

Bertacco

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Aggressive transistor scaling continues to drive increasingly complex digital designs. The large number of transistors available today enables the development of chip multiprocessors that include many cores on one die communicating through an on-chip interconnect. As the number of cores increases, scalable communication platforms, such as networks-on-chip (NoCs), have become more popular. However, as the sole communication medium, these interconnects are a single point of failure so that any permanent fault in the NoC can cause the entire system to fail. Compounding the problem, transistors have become increasingly susceptible to wear-out related failures as their critical dimensions shrink. As a result, the on-chip network has become a critically exposed unit that must be protected. To this end, we present Vicis, a fault-tolerant architecture and companion routing protocol that is robust to a large number of permanent failures, allowing communication to continue in the face of permanent transistor failures. Vicis makes use of a two-level approach. First, it attempts to work around errors within a router by leveraging reconfigurable architectural components. Second, when faults within a router disable a link's connectivity, or even an entire router, Vicis reroutes around the faulty node or link with a novel, distributed routing algorithm for meshes and tori. Tolerating permanent faults in both the router components and the reliability hardware itself, Vicis enables graceful performance degradation of networks-on-chip.

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A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

Cited by 107 publications

References 18 publications

Variable-width datapath for on-chip network static power reduction

Variable-width datapath for on-chip network static power reduction

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

A Reliable Routing Architecture and Algorithm for NoCs

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