A Reliable Routing Architecture and Algorithm for NoCs

Abstract

Abstract-Aggressive transistor scaling continues to drive increasingly complex digital designs. The large number of transistors available today enables the development of chip multiprocessors that include many cores on one die communicating through an on-chip interconnect. As the number of cores increases, scalable communication platforms, such as networks-on-chip (NoCs), have become more popular. However, as the sole communication medium, these interconnects are a single point of failure so that any permanent fault in the NoC can cause the entire system to fail. Compounding the problem, transistors have become increasingly susceptible to wear-out related failures as their critical dimensions shrink. As a result, the on-chip network has become a critically exposed unit that must be protected. To this end, we present Vicis, a fault-tolerant architecture and companion routing protocol that is robust to a large number of permanent failures, allowing communication to continue in the face of permanent transistor failures. Vicis makes use of a two-level approach. First, it attempts to work around errors within a router by leveraging reconfigurable architectural components. Second, when faults within a router disable a link's connectivity, or even an entire router, Vicis reroutes around the faulty node or link with a novel, distributed routing algorithm for meshes and tori. Tolerating permanent faults in both the router components and the reliability hardware itself, Vicis enables graceful performance degradation of networks-on-chip.

Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation

“…The hardware of the routers in the system is checked as frequently as the cores using tests that require 150 000 cycles [51]. Router's lists of local connections is kept updated much more frequently, every 10 000 cycles, to ensure correct communication between directly connected nodes.…”

“…Storage requirements grow linearly with system size, and thus Cardio benefits are even more marked for larger CMPs. When we consider both reconfigurable routing tables and router self-test logic, interconnect area increases by approximately 11.4% [51].…”

Brisk and limited-impact NoC routing reconfiguration

“…Upon a fault affecting a link (or a portion of a router impacting link operability) the disabled turns must be recomputed to allow packets to go through alternative surviving routes. This effort entails a global routing reconfiguration [4], and it does not guarantee deadlock-freedom. Up*/down* routing: Spanning tree-based routing algorithms, such as up*/down* routing [17], can be applied to route packets in any topology.…”

“…Most of them can be grouped into two families based on their approach to reconfiguration. The first family deploys routing tables and logic that are updated upon each fault occurrence [1,4,15,22]. This approach is topology-agnostic and, in the best case, it can tolerate an arbitrary number of faults, but suffers from high reconfiguration overhead.…”

“…Thus, rerouting entails recomputing the routing tables for all routers in the network [1,4,15]. We observe that we can limit the recomputation effort by utilizing pre-computed routing metadata, so to quickly pinpoint the affected routes.…”