Variable-width datapath for on-chip network static power reduction

Shalf, John

doi:10.1109/nocs.2014.7008767

Cited by 8 publications

(1 citation statement)

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“…By splitting each link and router to handle a subsection of the phit/flit width, the unused sections can be clock gated or power gated to improve efficiency. Similar ideas have been recently proposed for 2D networks to improve efficiency through clock and power gating by 25-45% [14,17], but the discrete nature of M3D tiers, with associated clock and power network subbranches, makes this partitioning and gating a natural, low-overhead design. It also ensures a regular, balanced usage of intermediate interconnect on each tier.…”

Section: Variable-width Links In M3d Nocmentioning

confidence: 97%

Efficient System Architecture in the Era of Monolithic 3D

Stow

Akgun

Huangfu

et al. 2019

Proceedings of the 56th Annual Design Automation Conference 2019

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Emerging Monolithic Three-Dimensional (M3D) integration technology will not only provide improved circuit density through the high-bandwidth coupling of multiple vertically-stacked layers, but it can also provide new architectural opportunities for on-chip computation, memory, and communication that are beyond the capabilities of existing process and packaging technologies. For example, with massive parallel communication between heterogeneous memory and compute layers, existing processing-in-memory architectures can be optimized and expanded, developing into efficient and flexible near-data processors. Additionally, multiple tiers of interconnect can be dynamically leveraged to provide an efficient, scalable interconnect fabric that spans the three-dimensional system. This work explores some of the challenges and opportunities presented by M3D technology for emerging computer architectures, with focus on improving efficiency and increasing system flexibility.

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Section: Variable-width Links In M3d Nocmentioning

confidence: 97%