A layout-based approach for ordering scan chain flip-flops

Makar, S.

doi:10.1109/test.1998.743172

Cited by 45 publications

(25 citation statements)

References 19 publications

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“…Several scan-based stuck-at fault test data compression methods have been proposed. These conventional works compress test data using conventional coding method 2), 3) , fan-out scan chain 4), 5) , seed encoding method 6) , or templatebased encoding method 7)-9) . These works are standard scan based one.…”

Section: Introductionmentioning

confidence: 99%

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability

Katoh

Namba

Ito

2008

IPSJ Transactions on System LSI Design Methodology

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This paper presents a stuck-at fault test data compression using the scan flip flops with delay fault testability namely the Chiba scan flip-flops. The feature of the proposed method is two-stage test data compression. First, test data is compressed utilizing the structure of the Chiba scan flip flops (the first stage compression). Second, the compressed test data is further compressed by conventional test data compression utilizing X bits (the second stage compression). Evaluation shows that when Huffman test data compression is used in the second stage compression, the volume of test data for the proposed test data compression in ATE is reduced 35.8% in maximum, 25.7% on average of the one of the test data compressed by the conventional method. The difference of the area overhead of the proposed method from the conventional method is 9.5 percent point.

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Section: Introductionmentioning

confidence: 99%

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability

Katoh

Namba

Ito

2008

IPSJ Transactions on System LSI Design Methodology

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“…While this overhead has received considerable attention in the context of stuck-at fault testing [3,5,6,8,12,15,17,18], previous works on scan synthesis for delay fault testing have focused on maximizing delay fault coverage without regard to any scan overheads [20], achieving a certain coverage factor with minimum number of dummy flip-flops but without regard of wirelength cost [7,21], or achieving full coverage regardless of a potentially high wirelength cost [11].…”

Section: Introductionmentioning

confidence: 99%

Layout-aware scan chain synthesis for improved path delay fault coverage

Gupta

Kahng

Măndoiu

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops in the scan chain. Previous works on scan synthesis for path delay fault testing using scan shifting have focused exclusively on maximizing fault coverage and/or minimizing the number of dummy flip-flops, but have disregarded the scan wirelength overhead. In this paper we consider both dummy flip-flop and wirelength costs, and focus on post-layout formulations that capture the achievable tradeoffs between these costs and delay fault coverage in scan chain synthesis.

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“…It should be noted that an alternative solution that specifies the exact scan chain ordering would increase the number of detected faults. However, fixing the scan chains without considering physical and routing constraints may not yield routable designs and is unacceptable from a synthesis standpoint [32]. Therefore, the groups of scan cells created by the selection algorithm are sent to the synthesis engine that creates the actual scan chains.…”

Section: Creating the Scan Chainsmentioning

confidence: 99%

A reconfigurable shared scan-in architecture

Samaranayake

Gizdarski²,

Sitchinava³

et al.

Proceedings. 21st VLSI Test Symposium, 2003.

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This thesis presents a test architecture for reducing the cost of testing an integrated circuit (IC). The cost of testing an IC is based on the volume of test data that needs to be loaded during the testing process and the time required to test the circuit. The proposed solution reduces both these factors using a new architecture to load test.data in parallel. Typically, test data is loaded into a circuit using chains of internal storage elements, called scan chains and each of these chains is connected to the inputs of the circuit under test. When loading the test data in parallel, many scan chains share the same input. The scan chains that share the same input must contain the same data, creating constraints on the test data that can be loaded. The constraints introduced increase as the number of chains that are loaded in parallel increases. Therefore, certain defects in a circuit might not be testable, if a large number of chains are loaded in parallel. The proposed architecture reduces the constraints of parallel loading by changing the inputs that drive each scan chain during the testing process. We call this change, reconfiguration of the scan chains. This thesis presents two methods of determining how to reconfigure the scan chains. The first method provides the largest gains, but requires a large amount of additional computation when creating the test data. Therefore, a second method that is less effective, but requires no additional computation is also presented. Experimental results show as much as a factor of 170 reductions in both the test time and test data volume relative to the standard serial testing.

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A layout-based approach for ordering scan chain flip-flops

Cited by 45 publications

References 19 publications

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability

Layout-aware scan chain synthesis for improved path delay fault coverage

A reconfigurable shared scan-in architecture

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