A reconfigurable shared scan-in architecture

Abstract

This thesis presents a test architecture for reducing the cost of testing an integrated circuit (IC). The cost of testing an IC is based on the volume of test data that needs to be loaded during the testing process and the time required to test the circuit. The proposed solution reduces both these factors using a new architecture to load test.data in parallel. Typically, test data is loaded into a circuit using chains of internal storage elements, called scan chains and each of these chains is connected to the inputs of the circuit under test. When loading the test data in parallel, many scan chains share the same input. The scan chains that share the same input must contain the same data, creating constraints on the test data that can be loaded. The constraints introduced increase as the number of chains that are loaded in parallel increases. Therefore, certain defects in a circuit might not be testable, if a large number of chains are loaded in parallel. The proposed architecture reduces the constraints of parallel loading by changing the inputs that drive each scan chain during the testing process. We call this change, reconfiguration of the scan chains. This thesis presents two methods of determining how to reconfigure the scan chains. The first method provides the largest gains, but requires a large amount of additional computation when creating the test data. Therefore, a second method that is less effective, but requires no additional computation is also presented. Experimental results show as much as a factor of 170 reductions in both the test time and test data volume relative to the standard serial testing.

A Unified Solution to Scan Test Volume, Time, and Power Minimization

“…Two scan cells are related by NCS if they cannot reach a common node in the circuit through combinational paths. Other researchers have used the complementary relation in defining a reconfigurable scan-chain architecture [21]. The usefulness of the NCS relation in minimizing correlation arises from the following lemma [20].…”

Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction

“…Since only one segment is controlled and observed at a time, the test data volume, test application time, and test power consumption are all reduced at once. A reconfigurable scheme that includes a mapping logic to control the connection of multiple scan chains was introduced in [9]. This method increases multiple scan chains compatibility to achieve additional compaction.…”

Scan Cell Positioning for Boosting the Compression of Fan-Out Networks

“…In every shift cycle, an n-bit stimulus is expanded into the m-bit fragment of the test vector (n < m), which is to be delivered into one of the scan slices as shown in Fig.1. Numerous test data compression techniques that have been proposed include the broadcast of the same data into all the scan chains through a single scanin pin [1−2] , the use of a linear decompression network, which can be combinational [3−4] or sequential [5] , decompression architectures in the form of a fan-out network [6−12] , and reconfigurable fan-out networks in the form of a Multiplexer (MUX) based [8] , XORbased [10] , or switch-based [11] network. The architecture in [9] offers further flexibility in switching from one fanout configuration to another between the shift cycles of the same test vector.…”