Layout-aware scan chain synthesis for improved path delay fault coverage

Gupta, Puneet; Kahng, Andrew B.; Măndoiu, Ion; Sharma, Puneet

doi:10.1109/tcad.2005.850900

Cited by 7 publications

(2 citation statements)

References 19 publications

(26 reference statements)

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“…In References [4,16,24,27,31,43], logic resynthesis techniques are used for improving the testability of the circuit by reducing the difficulty of test generation. In References [9,41,42], scan chain ordering is considered for improving the coverage for transition and path delay faults. With layout information taken into account, the routing penalty and the impact on circuit performance are limited.…”

Section: Introductionmentioning

confidence: 99%

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Wang

Pomeranz

Reddy

et al. 2019

ACM Trans. Des. Autom. Electron. Syst.

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Design-for-manufacturability (DFM) guidelines are recommended layout design practices intended to capture layout features that are difficult to manufacture correctly. Avoiding such features prevents the occurrence of potential systematic defects. Layout features that result in DFM guideline violations may not be avoided completely due to the design constraints of chip area, performance, and power consumption. A framework for translating DFM guideline violations into potential systematic defects, and faults, was described earlier.In a cell-based design, the translated faults may be internal or external to cells. In this article, we focus on undetectable faults that are external to cells. Using a resynthesis procedure that makes fine changes to the layout while maintaining the design constraints, we target areas of the design where large numbers of external faults related to DFM guideline violations are undetectable. By eliminating the corresponding DFM guideline violations, we ensure that the circuit does not suffer from low-coverage areas that may result in detectable systematic defects escaping detection, but failing the circuit in the field. The layout resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that the improvement in the coverage of potential systematic defects is significant.

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Section: Introductionmentioning

confidence: 99%

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Wang

Pomeranz

Reddy

et al. 2019

ACM Trans. Des. Autom. Electron. Syst.

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“…The scan flip-flops are reordered to minimize the number of undetectable faults due to test pattern dependency. Achieving high coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful reordering of scan flip-flops and/or insertion of dummy flip-flops in the scan chain [21]. The authors in [21] proposed a technique considering both the number of dummy flip-flops and wirelength costs to improve path delay fault coverage.…”

Section: B Related Prior Workmentioning

confidence: 99%

Improving transition delay fault coverage using hybrid scan-based technique

Ahmed

Tehranipoor

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

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Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction

Tsai

2008

IET Comput. Digit. Tech.

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Broadcast-based test compression techniques can reduce both test data and test time. However, the success of such methods heavily depends on the percentage of test patterns that can be broadcasted. In this paper, we first conduct a quantitative analysis that shows the simple broadcast architecture that cannot achieve good test time/data compression even under a test set with very high level of don't care bits. A multi-mode-segmented scan test architecture (MSSA) is then presented to solve the problem of low broadcast rate. Three operation modes are supported in this architecture: broadcast, multicast and serial. As a result, improved test data compression is achievable with limited hardware overhead, as serial-mode operations are largely eliminated. An algorithm for the two-way partitions of the scan segments is proposed to construct multicast mode configurations. Finally, we present a layout-aware scan chain ordering method to further improve test compression. The problem of ordering scan cells in multiple scan chains is mapped to a constrained standard cell placement problem in physical synthesis, and the simulated annealing method is used to solve the problem. The routing length of the scan chains are also taken into account in the ordering process

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Layout-aware scan chain synthesis for improved path delay fault coverage

Cited by 7 publications

References 19 publications

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Improving transition delay fault coverage using hybrid scan-based technique

Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction

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