A large, fast instruction window for tolerating cache misses

Lebeck, Alvin R.; Koppanalil, Jinson; Li, Tong; Patwardhan, Jaidev P.; Rotenberg, Eric

doi:10.1145/545214.545223

Cited by 109 publications

(104 citation statements)

References 40 publications

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“…However, several studies that do not need a multithreaded environment have been carried out more recently [20]- [24]. These studies commonly pre-execute instructions when the instruction window resources run out.…”

Section: Studies Considering Power On Mlp Exploitationmentioning

confidence: 99%

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Ando

Shioya

2016

IEICE Trans. Inf. & Syst.

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Hideki ANDO†a) and Ryota SHIOYA †b) , Members SUMMARY Dynamic instruction window resizing (DIWR) is a scheme that effectively exploits both memory-level parallelism and instruction-level parallelism by configuring the instruction window size appropriately for exploiting each parallelism. Although a previous study has shown that the DIWR processor achieves a significant speedup, power consumption has not been explored. The power consumption is increased in DIWR because the instruction window resources are enlarged in memoryintensive phases. If the power consumption exceeds the power budget determined by certain requirements, the DIWR processor must save power and thus, the performance previously presented cannot be achieved. In this paper, we explore to what extent the DIWR processor can achieve improved performance for a given power budget, assuming that dynamic voltage and frequency scaling (DVFS) is introduced as a power saving technique. Evaluation results using the SPEC2006 benchmark programs show that the DIWR processor, even with a constrained power budget, achieves a speedup over the conventional processor over a wide range of given power budgets. At the most important power budget point, i.e., when the power a conventional processor consumes without any power constraint is supplied, DIWR achieves a 16% speedup.

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Section: Studies Considering Power On Mlp Exploitationmentioning

confidence: 99%

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Ando

Shioya

2016

IEICE Trans. Inf. & Syst.

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“…Lebeck et al proposed a scheme that efficiently uses the IQ by moving a load causing an LLC miss and the instructions that depend directly or indirectly on it to a special buffer, called the WIB (waiting instruction buffer) [26]. MLP can be exploited in a small IQ.…”

Section: Exploiting Mlpmentioning

confidence: 99%

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism

Kora

Yamaguchi

Ando

2014

IEICE Trans. Inf. & Syst.

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SUMMARYSingle-thread performance has not improved much over the past few years, despite an ever increasing transistor budget. One of the reasons for this is that there is a speed gap between the processor and main memory, known as the memory wall. A promising method to overcome this memory wall is aggressive out-of-order execution by extensively enlarging the instruction window resources to exploit memory-level parallelism (MLP). However, simply enlarging the window resources lengthens the clock cycle time. Although pipelining the resources solves this problem, it in turn prevents instruction-level parallelism (ILP) from being exploited because issuing instructions requires multiple clock cycles. This paper proposed a dynamic scheme that adaptively resizes the instruction window based on the predicted available parallelism, either ILP or MLP. Specifically, if the scheme predicts that MLP is available during execution, the instruction window is enlarged and the window resources are pipelined, thereby exploiting MLP. Conversely, if the scheme predicts that less MLP is available, that is, ILP is exploitable for improved performance, the instruction window is shrunk and the window resources are de-pipelined, thereby exploiting ILP. Our evaluation results using the SPEC2006 benchmark programs show that the proposed scheme achieves nearly the best performance possible with fixed-size resources. On average, our scheme realizes a performance improvement of 21% over that of a conventional processor, with additional cost of only 6% of the area of the conventional processor core or 3% of that of the entire processor chip. The evaluation results also show 8% better energy efficiency in terms of 1/EDP (energy-delay product).

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“…Work in this field has concentrated on the reorder buffer [7,1], the instruction queues [7,16,30], on handling registers [19,6] and on the load/store queue. Load queue resource requirements can be greatly reduced by using techniques for early release of load instructions [8,18].…”

Section: Related Workmentioning

confidence: 99%

“…Otherwise they have low execution locality. This observation enables the construction of large-window processors requiring only moderately-sized structures by focusing only on the execution of high locality code [7,16,30,23].…”

Section: Recent Trends In Ilp Processorsmentioning

confidence: 99%