A K-band area-saving marchand balun integrated with low-noise amplifier in 0.18-μm CMOS

Chen, Hong-Shen; Wu, Chunyong; Lin, Yi-Cheng; Liu, Jenny Yi-Chun

doi:10.1109/apmc.2017.8251673

Cited by 5 publications

(2 citation statements)

References 10 publications

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“…Various on-chip passive baluns are proposed in [24,25,26,27,28,29,30,31]. In this design, an area-saving and performance improvement transformer balun with center open stub is presented.…”

Section: Input Passive Balunmentioning

confidence: 99%

A 6–18 GHz 6-bit active phase shifter in 0.13-µm SiGe BiCMOS

Luo

Yao

et al. 2019

IEICE Electron. Express

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A 6-bit digitally controlled active phase shifter is implemented in 0.13-µm SiGe BiCMOS process for 6-18 GHz phased-arrays. An input passive balun with center open stub is applied to split the single input to differential and achieve high amplitude/phase balance. A degenerated-Q quadrature all-pass filter (QAF) is used to generate two orthogonal vectors with high I/Q accuracy over a wide bandwidth and a main digital-toanalog convertor (DAC) controls the I/Q amplitude to achieve 6-bit phase resolution. In addition, a calibration DAC is adopted to compensate the amplitude variations and the phase error introduced by balun and QAF. Consequently, high resolution along with low gain/phase error can be achieved. The phase shifter has achieved root mean square (RMS) phase error of <4.36°, and RMS gain error of <1.04 dB for all 6-bit phase states at 6-18 GHz. The power gain ranges from 0.95 dB at 6 GHz to −1.85 dB at 18 GHz. Input 1 dB compression point (IP −1dB) is 5.4-8 dBm at 6-18 GHz for 0°-phase state. The total power consumption is 74.4 mW, and the overall chip size is 1.8 × 1.3 mm 2 .

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“…Various on-chip passive baluns are proposed in [24,25,26,27,28,29,30,31]. In this design, an area-saving and performance improvement transformer balun with center open stub is presented.…”

Section: Input Passive Balunmentioning

confidence: 99%

A 6–18 GHz 6-bit active phase shifter in 0.13-µm SiGe BiCMOS

Luo

Yao

et al. 2019

IEICE Electron. Express

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“…In a beamformer IC, the input-output (I/O) of antenna ports is single-ended because of the unbalanced structure of antennas [3], and components in receivers typically use differential topology to reduce noise; therefore, single-input differential-output (SIDO) low-noise amplifiers (LNAs) [4], [5], [6], [7], [8], [9], [10] have been used to connect antennas and differential components in communication systems [10]. However, designing an LNA with simultaneous multiband and SIDO is challenging.…”

Section: Introductionmentioning

confidence: 99%

Ka-/K-Band Frequency-Reconfigurable Single-Input Differential-Output Low-Noise Amplifier for 5G Applications

Chen

Tsai

2023

IEEE Microw. Wireless Tech. Lett.

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This letter describes the design, analysis, and performance measurements of a K a-and K -band frequencyreconfigurable single-input differential-output (SIDO) low-noise amplifier (LNA) with a compact core size of 0.157 mm 2 . At 28 and 39 GHz, respectively, the noise figures of the LNA were 2.8 and 4.4 dB; it had high differential gains of 20.1 and 14.9 dB. The proposed LNA was fabricated using the 65-nm CMOS process. The LNA includes a two-stage common-source (CS) buffer amplifier to achieve low noise and an active balun for converting single-ended signals into differential signals. Moreover, a substrate-shield-based inductor and tunable matching networks were used to achieve the frequency reconfiguration function of the LNA. The gain and phase imbalances were 0.3 and 0.2 dB, and 5.4 • and 6 • at 28 and 39 GHz, respectively. Compared with published multiband SIDO LNAs, the proposed amplifier achieved higher figures of merit (FoMs) of 3.52 and 1.77 while maintaining a compact core size. Therefore, the LNA is suitable for K -and K a-band 5G communication applications.

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