A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)

Gjanci, J.; Chowdhury, Masud H.

doi:10.1109/tvlsi.2010.2072997

Cited by 23 publications

(16 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Some researchers also investigated the implementation of a hybrid power delivery systems with off/on-chip regulators. Gjanci et al proposed a hybrid two-stage voltage regulation scheme with off-chip switching regulators and onchip linear regulators [26]. Vaisband et al also investigated the methodology of a heterogeneous power delivery system with off-chip switching regulators and up to 100 on-chip point-ofload linear regulators [27].…”

Section: Related Workmentioning

confidence: 99%

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors

Wang

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

The design of power delivery system plays a crucial role in guaranteeing the proper functionality of many-core processor systems. The power loss suffered on power delivery has become a salient part of total power consumption, and the energy efficiency of a highly dynamic system has been significantly challenged. Being able to achieve a fast response time and multiple voltage domain control, on-chip voltage regulators(VRs) have become popular choices to enable fine-grain power management, which also enlarge the design space of power delivery systems. This paper analytically studies different power delivery system paradigms and power management schemes in terms of energy efficiency, area overhead and power pin occupation. The analysis shows that compared to the conventional paradigm with offchip voltage regulators, hybrid paradigms with both on-chip and off-chip voltage regulators are able to maintain high efficiency in a larger range of workloads, though they suffer from low efficiency at light workload. Employed with the quantized power management scheme, the hybrid paradigm can improve the system energy efficiency at light workload by a maximum of 136% compared to the traditional load balanced scheme. Besides this, the in-package hybrid paradigm further shows its advantage in reducing the physical overheads. The results reveal that at 120W workload, it occupies only a 10.94% total footprint area or 39.07% power pins of that of the off-chip paradigm. We conclude that the in-package hybrid paradigm achieves the best trade-offs between efficiency, physical overhead and realization of fine-grain power management.Index Terms-power delivery system, voltage regulator, energy efficiency, power management, package pins

show abstract

Section: Related Workmentioning

confidence: 99%

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors

Wang

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…It demonstrated the potential benefits of improving the system power consumption by providing fine-grained power management and fast voltage scaling. Gjanci et al proposed a hybrid two-stage power delivery system with off-chip buck converters and a tree structure of on-chip linear regulators, which was able to be efficient, simple and small area costly [18]. Yan et al presented an application-aware scheduling strategy to dynamically utilize the on-chip converters for the dynamic voltage scaling sensitive applications with limited area overhead of on-chip converters [19].…”

Section: Introductionmentioning

confidence: 99%

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators

Wang

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Design of power delivery system has great influence on the power management in many-core processor systems. Moving voltage regulators from off-chip to on-chip gains more and more interest in the power delivery system design, because it is able to provide fine-grained dynamic voltage scaling. Previous works are proposed to implement power efficient on-chip voltage regulators. It is important to analyze the characteristics of the entire power delivery system to explore the tradeoff between the promising properties and costs of employing on-chip voltage regulators, especially the on-chip buck converters. In this work, we present a novel analysis and design optimization platform of power delivery system called PowerSoC. It employs an analytical model to provide an accurate and fast evaluation of important characteristics, e.g. power efficiency, output stability and dynamic voltage scaling, for the entire power delivery system consisting of on-chip/off-chip buck converters and power delivery network. Based on our model, geometric programming is utilized to find the optimal design for different power delivery systems and explore the tradeoff of using on-chip converters. Compared with SPICE simulations, our model achieves a simulation time reduction of six to seven orders of magnitude within 5% model error for the characteristic evaluation of different power delivery systems. By using PowerSoC, various architectures of power delivery systems are optimized for power efficiency under constraints of output stability, area, etc. Simulation results show compared with the conventional architecture, the hybrid one using both on-chip and off-chip converters achieves 1.0% power efficiency improvement and 66.4% area reduction of converters on average. We conclude the hybrid architecture has potential for efficient dynamic voltage scaling, small area and the adaptability of the change of power delivery network parasitic, but careful account for the overhead of on-chip converters is needed.

show abstract

“…Several schemes for heterogeneous power delivery [29,8,[30][31][32] that consider tens to hundreds of on-chip power regulators have Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/vlsi recently been proposed. Optimizing the power delivery process in terms of the co-design of the on-chip voltage regulators, decoupling capacitors, and current loads have been proposed in [29,8,[30][31][32].…”

Section: Introductionmentioning

confidence: 99%

“…Optimizing the power delivery process in terms of the co-design of the on-chip voltage regulators, decoupling capacitors, and current loads have been proposed in [29,8,[30][31][32]. The stability of a distributed power delivery system where several power supplies drive the same low impedance power grid is an additional concern, and should be addressed as power delivery systems become more complicated with multiple on-chip power regulators operating off the same grid.…”

Section: Introductionmentioning

confidence: 99%