A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

Chen, Shih-Hung; Lue, Hang-Ting; Shih, Yung‐Feng; Chen, Chieh-Fang; Hsu, Tzu-Hsuan; Chen, Yanru; Hsiao, Yi‐Hsuan; Huang, Shih-Cheng; Chang, Kai‐Chun; Hsieh, Chih-Chang; Lee, Guan-Ru; Chuang, Alfred-Tung-Hua; Hu, Chih‐Wei; Chiu, Chia-Jung; Lin, Lo Yueh; Lee, Hong-Ji; Tsai, Fengnien; Yang, Chin-Cheng; Yang, Tahone; Lu, Chih‐Yuan

doi:10.1109/iedm.2012.6478963

Cited by 32 publications

(16 citation statements)

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“…2D NAND-type Flash has already scaled to 16 nm node, whereas scaling to near 10 nm seems possible [2]. Further density scaling, though, may require a different memory technology and/or a 3D architecture, and 3D NAND Flash is currently being developed [51]. Current projections for the achievable packing density (bits/cm 2 ) of ReRAM remain substantially lower than those for 3D NAND Flash, unless 3D ReRAM is fabricated [9].…”

Section: Overview and Discussionmentioning

confidence: 97%

Memristive Crossbar-Based Nonvolatile Memory

Vourkas

Sirakoulis

2015

Emergence, Complexity and Computation

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Section: Overview and Discussionmentioning

confidence: 97%

Memristive Crossbar-Based Nonvolatile Memory

Vourkas

Sirakoulis

2015

Emergence, Complexity and Computation

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“…The 3D Vertical Gate (3D VG-type) NAND architecture (Horizontal Channel structure) has been investigated and extensively studied, being the following references only a small example of related publications [8,10,[18][19][20][21][22][23][24][25]. The scalability of the architecture has been studied down to the 2× nm node.…”

Section: Vg-type 3d Nand Architecturementioning

confidence: 99%

“…The main contributors have been Toshiba [1][2][3], Samsung [4][5][6][7], Macronix [8][9][10], Hynix [11][12][13], Micron [14] amongst the Memory companies. The main scope of 3D development was lowering the cost per bit and increase the chip density without shrinking the 2D lithography node.…”

Section: D Nand Architecturesmentioning

confidence: 99%

3D VG-Type NAND Flash Memories

Silvagni

2016

3D Flash Memories

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Solid State Disk applications have been the main drivers for the cost reduction of NAND Flash memory. Technology scaling limits have been almost reached and new directions were investigated for a decade. 3D NAND appeared as the most promising and short term viable solution to the scaling problem. 3D NAND offers the possibility to keep scaling memory density beyond 2D NAND 1z nm technology and opens new landscapes if the technology hurdles can be definitely overcome. Additionally Multi bit per cell technology is applicable to 3D NAND as well; therefore, the storage capacity growth trend is not going to meet the inflection point soon. Big Data storage demand remains certainly the driver for the rapidity of 3D NAND to become industry mainstream.With respect to the flat 2D NAND Flash, three-dimensional architectures demand a more challenging approach to deal with process, design architectures, parasitic effects, testing. At the time of writing this chapter, 3D technology is moving into production inside solid state storage solutions; however, those NAND chips aren't commercially available as raw components. 3D NAND chips are used by vertically integrated manufacturers and few partners to build the storage systems under a strict control on the usage. Technology solutions are still diversified among the few players in the 3D arena and no unique mainstream solution is emerged yet.In this chapter the principal architectural pieces of 3D NAND will be reviewed putting the focus on one of them: VG-Type, Vertical Gate 3D NAND.

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“…For VG 3D NAND, the formation of the strings is quite straightforward; the wordline and sourceline resistance is managed easily, however the connection to the bitline and the string selection is more complicated compared to vertical channel. In [29,30] a simple method for SSL transistor formation is proposed; this is a special connecting structure from the horizontal polysilicon string channels to the metal bitlines, and it optimizes the layout of the select transistors. Figure 11.…”

Section: Vertical Gate-type Architecturesmentioning

confidence: 99%

“…A split-gate architecture was also proposed in order to relax the lithography on the select gates (split-gate architecture). Several other innovations have led to a very compact layout of the VG NAND and its operation [29][30][31][32].…”

Section: Single-gate Vertical Channel (Sgvc) Architecturementioning

confidence: 99%

3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

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Abstract:In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a "punch-and-plug" process-with gate-all-around (GAA) cell devices-against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.

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A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

Cited by 32 publications

References 1 publication

Memristive Crossbar-Based Nonvolatile Memory

Memristive Crossbar-Based Nonvolatile Memory

3D VG-Type NAND Flash Memories

3D NAND Flash Based on Planar Cells

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