A high speed low jitter LVDS output driver for serial links

Lv, Junsheng; Ju, Hu; Li, Yuan; Zhao, Jianzhong; Zhang, Feng; Wu, Bin; Jiang, Jianhua; Zhou, Yumei

doi:10.1007/s10470-011-9658-x

Cited by 8 publications

(7 citation statements)

References 5 publications

(3 reference statements)

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“…It employs differential data transmission and the receiver is configured as a switched-polarity signal generator. The receiver is composed of a pre-stage common mode voltage (Vcm) shifter and a rail-to-rail comparator (COMP), while the transmitter includes a CMOS H-bridge output driver with a common mode feedback (CMFB) circuit, a high- In general, the architecture of LVDS drivers is divided into fully-differential NMOS-only style [12], fully-differential PMOS-only style [13] and complementary MOS style [14][15][16]. As shown in Figure 2, all configurations consist of four MOS switches arranged in an H-bridge structure.…”

Section: Architecture Designmentioning

confidence: 99%

“…In addition, the wide common mode input of LVDS makes its devices easily interoperable with other differential signaling technologies [9][10][11]. In general, the architecture of LVDS drivers is divided into fully-differential NMOS-only style [12], fully-differential PMOS-only style [13] and complementary MOS style [14][15][16]. As shown in Figure 2, all configurations consist of four MOS switches arranged in an H-bridge structure.…”

Section: Introductionmentioning

confidence: 99%

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A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

et al. 2019

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This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 ps@2.5 Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

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Section: Architecture Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

et al. 2019

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“… presents an adaptable energy‐efficient differential transceiver for 2.5D TSI achieving 4Gbps at 13‐mW power consumption. Similarly, another LVDS transceiver has been shown to support around 1Gbps rate using 0.35‐µm CMOS at 23 mW and up to 2.15Gbps on 0.25‐µm CMOS technique at 37 mW. A 12.8Gbps/link model single‐ended terminated memory interface has been demonstrated for 35.7 mW/Gbps energy efficiency by achieving 40 Ω of driver impedance to match the channel's intrinsic impedance on the PCB in TSMC 40‐nm CMOS process .…”

Section: Introductionmentioning

confidence: 99%

IO circuit design for 2.5D through‐silicon‐interposer interconnects

Jawed

Afridi

Anjum

et al. 2016

Circuit Theory & Apps

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This paper presents four topologies of voltage-mode un-terminated IO cells in 28-nm CMOS for singleended rail-to-rail signaling over a passive interposer die in 2.5D configuration for >1Gbps data rates. The presented design explores the existing IO design-space from a 2.5D viewpoint, optimizing existing topologies from area, speed, power and protection perspectives, with a higher degree of configurability in the form of pre-emphasis and slew-rate control. The transmitter (TX) embeds pre-emphasis to enhance high-frequency components of the signal for longer low-pass natured channels. The TX also implements slew-rate control to minimize reflections on shorter channels because of impedance discontinuities and also to minimize simultaneous switching noise. Level-shifting capability embedded in the receiver (RX) enables multi-technology interfacing where different dies are signaling at their core voltages (range: 0.7 V-1.8 V) instead of following a particular signaling standard. The measurement results of the transceivers, over a interposer of length of 3.5 mm, demonstrate ±5% duty-cycle distortion with 700 μW at 500 MHz/0.8-V-signaling on the channel with jitter of 20 ps, ±10% duty-cycle distortion with 1.8 mW at 1Gbps/0.9-V signaling with jitter of 20 ps, ±10% duty-cycle distortion with 2 mW at 2Gbps/0.7-V signaling for 1-V receiver core voltage with a jitter of 10 ps. of limiter material or functional errors because of electro-thermal coupling or excessive leakage currents which can form a positive feedback loop with the temperature leading to thermal run-away problem [10,11]. Moreover, the thermal expansion coefficients of TSV material and substrate are different, which can result in large temperature induced mechanical stress again leading to nonuniform distribution of delay across the area [5].Recently, 2.5D IC stacking has emerged as a viable alternative because of its higher mechanical and thermal reliability with a comparable interconnect density [10,12,13]. Several flip-chip dies are attached with fine-pitch micro-bumps to a single passive interposer die also known as throughsilicon-interposer (TSI) communication. This interposer die allows connections between adjacently placed multi-technology dies as well as connections to the package, providing low interconnect delay, high-bandwidth, multi-technology interfacing and reduced ESD protection requirements for die-to-die connections [14]. Moreover, although incurring the cost of adding a passive Si interposer, TSI avoids the issues faced by TSV based 3D configuration related to the high-temperature gradients because of poor thermal distribution, difficult IO planning, large keep-out areas and reliable manufacturing [10,13,15,16]. When compared with traditional backplane through-PCB interconnections which span lengths of few inches (>25 cm), TSI interconnects are much shorter (few mm) in length [2], which is one of the main reasons for their enhanced performance. For example, at 5 Gbps a 25-cm-long PCB track suffers from approximately 20-dB additional channel l...

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“…There are generally two different types of output drivers in a transmitter: voltage‐mode (VM) and current‐mode (CM) . The principle circuit of a two‐tap pre‐emphasis VM output driver is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Additionally, the switches implemented by the MOS transistors have a large size to achieve small impedance, which results in large output parasitic capacitor to be driven. These problems will finally degrade the SI and power efficiency of the VM output driver .…”

Section: Introductionmentioning

confidence: 99%

A 5‐Gbps low‐power low‐jitter voltage‐mode transmitter with two‐tap pre‐emphasis and impedance calibration in 65‐nm CMOS

Tian

Song

2016

IEEJ Transactions Elec Engng

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A low-power low-jitter voltage-mode (VM) transmitter with two-tap pre-emphasis and impedance calibration for high-speed serial links is presented. Based on a comprehensive analysis of the relationship between impedance, supply current, and preemphasis of the output driver, an impedance control circuit (ICU) is presented to maintain the 50 output impedance and suppress the reflection, a self-biased regulator is proposed to regulate the power supply, and an edge driver is introduced to speed up the signal transition time. Therefore, the signal integrity (SI) of the transmitter is improved with low power consumption. The whole transmitter is implemented in 65-nm CMOS technology. It provides an eye height greater than 688 mV at the far end with a root-mean-squared jitter of less than 6.99 ps at 5 Gbps. The transmitter consumes 15.2 mA and occupies only 370 μm × 230 μm.

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A high speed low jitter LVDS output driver for serial links

Cited by 8 publications

References 5 publications

A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

IO circuit design for 2.5D through‐silicon‐interposer interconnects

A 5‐Gbps low‐power low‐jitter voltage‐mode transmitter with two‐tap pre‐emphasis and impedance calibration in 65‐nm CMOS

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