A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator

Abstract

Resistive random access memory (RRAM)-based neuromorphic hardware accelerators are attractive platforms for neural network acceleration due to their high energy efficiency. However, the inherent variations of RRAM, arising from diffusion or recombination of oxygen vacancies, can cause significant conductance deviation from the target value, resulting in noticeable performance degradation. In practical ex situ training, write-verify methods are widely adopted to avoid this issue when transferring a trained network model. However, the intense reading and reprogramming operations make the conventional write-verify methods require extensive programming time and energy. In this brief, for the first time, we propose a novel writeverify scheme that can transfer each weight with a different acceptable error margin to achieve a high-speed and highefficiency write-verify scheme while maintaining network performance. Our experimental results show that the speed and energy efficiency of the write-verify process can be improved significantly, by up to ×3.4∼×9.0 and ×4.1∼×14.1, respectively.

Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture

“…Several approaches have been proposed to solve the readdisturb problem in RRAM-based CIM architecture. For in-stance, employing a low read voltage can reduce the impact of conductance drifts [10], [11]. Nevertheless, the voltage reduction can also increase the rate of incorrect computations, especially in the presence of process variation.…”