A High-Speed 850-nm Optical Receiver Front-End in 0.18-<tex>$muhbox m$</tex>CMOS

Abstract

A high-speed optical interface circuit for 850-nm optical communication is presented. Photodetector, transimpedance amplifier (TIA), and post-amplifier are integrated in a standard 0.18-m 1.8-V CMOS technology. To eliminate the slow substrate carriers, a differential n-well diode topology is used. Device simulations clarify the speed advantage of the proposed diode topology compared to other topologies, but also demonstrate the speed-responsivity tradeoff. Due to the lower responsivity, a very sensitive transimpedance amplifier is needed. At 500 Mb/s, an input power of 8 dBm is sufficient to have a bit error rate of 3 10 10. Next, the design of a broadband post-amplifier is discussed. The small-signal frequency dependent gain of the traditional and modified Cherry-Hooper stage is analyzed. To achieve broadband operation in the output buffer, so-called " doublers" are used. For a differential 10 mV pp 2 31 1 pseudo random bit sequence, a bit error rate of 5 10 12 at 3.5 Gb/s has been measured. At lower bit-rates, the bit error rate is even lower: a 1-Gb/s 10-mV pp input signal results in a bit error rate of 7 10 14. The TIA consumes 17 mW, while the post-amplifier circuit consumes 34 mW.

A Bandwidth Enhanced Transimpedance Amplifier with Improved Noise Performance

“…In [1,5] it is shown that this is the best choice in terms of responsivity and parasitic capacitance. The latter figure is the one of interest here as the proposed topology aims at reducing its detrimental effect.…”

“…This technique requires the ability to access both the cathode and the anode of the photodiode. For an integrated photodiode in standard CMOS, the best choice for the p-type material is the p-substrate [1,5]. As the substrate is grounded, this technique is not applicable for receivers with an integrated photodiode.…”

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

“…In these applications, short wavelength vertical-cavity surface-emitting lasers (VCSELs) and silicon (Si) photodiodes (PDs) are used for low-cost system configuration. Si PDs fabricated by CMOS process are promising optical devices for easy integration with electronic circuits without any process modification [4][5][6], and avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have been developed for optical interconnection applications [7][8][9][10]. The bandwidth of the CMOS-APD, however, is limited by slow photo-generated carriers from the substrate because all the electrodes are arranged on the surface of the substrate.…”

A 1–13 Gbps tunable optical receiver with supply voltage scaling

“…In the optical receiver, the optimum bandwidth can be determined as per the target bitrates. The rule of thumb for the best bit error rate (BER), considering tradeoffs between inter-symbol interference (ISI) and noise, is that the optimum bandwidth is 0.7 times the target bitrate [1]. Therefore, when the target bitrate changes or wide-band operations are required, the optical receiver needs to have a tuning ability in terms of bandwidth.…”